00001 #ifndef _GPXE_ATA_H 00002 #define _GPXE_ATA_H 00003 00004 #include <stdint.h> 00005 #include <gpxe/blockdev.h> 00006 #include <gpxe/uaccess.h> 00007 #include <gpxe/refcnt.h> 00008 00009 /** @file 00010 * 00011 * ATA devices 00012 * 00013 */ 00014 00015 FILE_LICENCE ( GPL2_OR_LATER ); 00016 00017 /** 00018 * An ATA Logical Block Address 00019 * 00020 * ATA controllers have three byte-wide registers for specifying the 00021 * block address: LBA Low, LBA Mid and LBA High. This allows for a 00022 * 24-bit address. Some devices support the "48-bit address feature 00023 * set" (LBA48), in which case each of these byte-wide registers is 00024 * actually a two-entry FIFO, and the "previous" byte pushed into the 00025 * FIFO is used as the corresponding high-order byte. So, to set up 00026 * the 48-bit address 0x123456abcdef, you would issue 00027 * 00028 * 0x56 -> LBA Low register 00029 * 0xef -> LBA Low register 00030 * 0x34 -> LBA Mid register 00031 * 0xcd -> LBA Mid register 00032 * 0x12 -> LBA High register 00033 * 0xab -> LBA High register 00034 * 00035 * This structure encapsulates this information by providing a single 00036 * 64-bit integer in native byte order, unioned with bytes named so 00037 * that the sequence becomes 00038 * 00039 * low_prev -> LBA Low register 00040 * low_cur -> LBA Low register 00041 * mid_prev -> LBA Mid register 00042 * mid_cur -> LBA Mid register 00043 * high_prev -> LBA High register 00044 * high_cur -> LBA High register 00045 * 00046 * Just to complicate matters further, in non-LBA48 mode it is 00047 * possible to have a 28-bit address, in which case bits 27:24 must be 00048 * written into the low four bits of the Device register. 00049 */ 00050 union ata_lba { 00051 /** LBA as a 64-bit integer in native-endian order */ 00052 uint64_t native; 00053 /** ATA registers */ 00054 struct { 00055 #if __BYTE_ORDER == __LITTLE_ENDIAN 00056 uint8_t low_cur; 00057 uint8_t mid_cur; 00058 uint8_t high_cur; 00059 uint8_t low_prev; 00060 uint8_t mid_prev; 00061 uint8_t high_prev; 00062 uint16_t pad; 00063 #elif __BYTE_ORDER == __BIG_ENDIAN 00064 uint16_t pad; 00065 uint8_t high_prev; 00066 uint8_t mid_prev; 00067 uint8_t low_prev; 00068 uint8_t high_cur; 00069 uint8_t mid_cur; 00070 uint8_t low_cur; 00071 #else 00072 #error "I need a byte order" 00073 #endif 00074 } bytes; 00075 }; 00076 00077 /** An ATA 2-byte FIFO register */ 00078 union ata_fifo { 00079 /** Value in native-endian order */ 00080 uint16_t native; 00081 /** ATA registers */ 00082 struct { 00083 #if __BYTE_ORDER == __LITTLE_ENDIAN 00084 uint8_t cur; 00085 uint8_t prev; 00086 #elif __BYTE_ORDER == __BIG_ENDIAN 00087 uint8_t prev; 00088 uint8_t cur; 00089 #else 00090 #error "I need a byte order" 00091 #endif 00092 } bytes; 00093 }; 00094 00095 /** ATA command block */ 00096 struct ata_cb { 00097 /** Logical block address */ 00098 union ata_lba lba; 00099 /** Sector count */ 00100 union ata_fifo count; 00101 /** Error/feature register */ 00102 union ata_fifo err_feat; 00103 /** Device register */ 00104 uint8_t device; 00105 /** Command/status register */ 00106 uint8_t cmd_stat; 00107 /** LBA48 addressing flag */ 00108 int lba48; 00109 }; 00110 00111 /** Obsolete bits in the ATA device register */ 00112 #define ATA_DEV_OBSOLETE 0xa0 00113 00114 /** LBA flag in the ATA device register */ 00115 #define ATA_DEV_LBA 0x40 00116 00117 /** Slave ("device 1") flag in the ATA device register */ 00118 #define ATA_DEV_SLAVE 0x10 00119 00120 /** Master ("device 0") flag in the ATA device register */ 00121 #define ATA_DEV_MASTER 0x00 00122 00123 /** Mask of non-LBA portion of device register */ 00124 #define ATA_DEV_MASK 0xf0 00125 00126 /** "Read sectors" command */ 00127 #define ATA_CMD_READ 0x20 00128 00129 /** "Read sectors (ext)" command */ 00130 #define ATA_CMD_READ_EXT 0x24 00131 00132 /** "Write sectors" command */ 00133 #define ATA_CMD_WRITE 0x30 00134 00135 /** "Write sectors (ext)" command */ 00136 #define ATA_CMD_WRITE_EXT 0x34 00137 00138 /** "Identify" command */ 00139 #define ATA_CMD_IDENTIFY 0xec 00140 00141 /** An ATA command */ 00142 struct ata_command { 00143 /** ATA command block */ 00144 struct ata_cb cb; 00145 /** Data-out buffer (may be NULL) 00146 * 00147 * If non-NULL, this buffer must be ata_command::cb::count 00148 * sectors in size. 00149 */ 00150 userptr_t data_out; 00151 /** Data-in buffer (may be NULL) 00152 * 00153 * If non-NULL, this buffer must be ata_command::cb::count 00154 * sectors in size. 00155 */ 00156 userptr_t data_in; 00157 /** Command status code */ 00158 int rc; 00159 }; 00160 00161 /** 00162 * Structure returned by ATA IDENTIFY command 00163 * 00164 * This is a huge structure with many fields that we don't care about, 00165 * so we implement only a few fields. 00166 */ 00167 struct ata_identity { 00168 uint16_t ignore_a[60]; /* words 0-59 */ 00169 uint32_t lba_sectors; /* words 60-61 */ 00170 uint16_t ignore_b[21]; /* words 62-82 */ 00171 uint16_t supports_lba48; /* word 83 */ 00172 uint16_t ignore_c[16]; /* words 84-99 */ 00173 uint64_t lba48_sectors; /* words 100-103 */ 00174 uint16_t ignore_d[152]; /* words 104-255 */ 00175 }; 00176 00177 /** Supports LBA48 flag */ 00178 #define ATA_SUPPORTS_LBA48 ( 1 << 10 ) 00179 00180 /** ATA sector size */ 00181 #define ATA_SECTOR_SIZE 512 00182 00183 /** An ATA device */ 00184 struct ata_device { 00185 /** Block device interface */ 00186 struct block_device blockdev; 00187 /** Device number 00188 * 00189 * Must be ATA_DEV_MASTER or ATA_DEV_SLAVE. 00190 */ 00191 int device; 00192 /** LBA48 extended addressing */ 00193 int lba48; 00194 /** 00195 * Issue ATA command 00196 * 00197 * @v ata ATA device 00198 * @v command ATA command 00199 * @ret rc Return status code 00200 */ 00201 int ( * command ) ( struct ata_device *ata, 00202 struct ata_command *command ); 00203 /** Backing device */ 00204 struct refcnt *backend; 00205 }; 00206 00207 extern int init_atadev ( struct ata_device *ata ); 00208 00209 #endif /* _GPXE_ATA_H */
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