amd8111e.h File Reference

Go to the source code of this file.

Defines

#define ASF_STAT   0x00
#define CHIPID   0x04
#define MIB_DATA   0x10
#define MIB_ADDR   0x14
#define STAT0   0x30
#define INT0   0x38
#define INTEN0   0x40
#define CMD0   0x48
#define CMD2   0x50
#define CMD3   0x54
#define CMD7   0x64
#define CTRL1   0x6C
#define CTRL2   0x70
#define XMT_RING_LIMIT   0x7C
#define AUTOPOLL0   0x88
#define AUTOPOLL1   0x8A
#define AUTOPOLL2   0x8C
#define AUTOPOLL3   0x8E
#define AUTOPOLL4   0x90
#define AUTOPOLL5   0x92
#define AP_VALUE   0x98
#define DLY_INT_A   0xA8
#define DLY_INT_B   0xAC
#define FLOW_CONTROL   0xC8
#define PHY_ACCESS   0xD0
#define STVAL   0xD8
#define XMT_RING_BASE_ADDR0   0x100
#define XMT_RING_BASE_ADDR1   0x108
#define XMT_RING_BASE_ADDR2   0x110
#define XMT_RING_BASE_ADDR3   0x118
#define RCV_RING_BASE_ADDR0   0x120
#define PMAT0   0x190
#define PMAT1   0x194
#define XMT_RING_LEN0   0x140
#define XMT_RING_LEN1   0x144
#define XMT_RING_LEN2   0x148
#define XMT_RING_LEN3   0x14C
#define RCV_RING_LEN0   0x150
#define SRAM_SIZE   0x178
#define SRAM_BOUNDARY   0x17A
#define PADR   0x160
#define IFS1   0x18C
#define IFS   0x18D
#define IPG   0x18E
#define LADRF   0x168
#define PHY_SPEED_10   0x2
#define PHY_SPEED_100   0x3
#define rcv_miss_pkts   0x00
#define rcv_octets   0x01
#define rcv_broadcast_pkts   0x02
#define rcv_multicast_pkts   0x03
#define rcv_undersize_pkts   0x04
#define rcv_oversize_pkts   0x05
#define rcv_fragments   0x06
#define rcv_jabbers   0x07
#define rcv_unicast_pkts   0x08
#define rcv_alignment_errors   0x09
#define rcv_fcs_errors   0x0A
#define rcv_good_octets   0x0B
#define rcv_mac_ctrl   0x0C
#define rcv_flow_ctrl   0x0D
#define rcv_pkts_64_octets   0x0E
#define rcv_pkts_65to127_octets   0x0F
#define rcv_pkts_128to255_octets   0x10
#define rcv_pkts_256to511_octets   0x11
#define rcv_pkts_512to1023_octets   0x12
#define rcv_pkts_1024to1518_octets   0x13
#define rcv_unsupported_opcode   0x14
#define rcv_symbol_errors   0x15
#define rcv_drop_pkts_ring1   0x16
#define rcv_drop_pkts_ring2   0x17
#define rcv_drop_pkts_ring3   0x18
#define rcv_drop_pkts_ring4   0x19
#define rcv_jumbo_pkts   0x1A
#define xmt_underrun_pkts   0x20
#define xmt_octets   0x21
#define xmt_packets   0x22
#define xmt_broadcast_pkts   0x23
#define xmt_multicast_pkts   0x24
#define xmt_collisions   0x25
#define xmt_unicast_pkts   0x26
#define xmt_one_collision   0x27
#define xmt_multiple_collision   0x28
#define xmt_deferred_transmit   0x29
#define xmt_late_collision   0x2A
#define xmt_excessive_defer   0x2B
#define xmt_loss_carrier   0x2C
#define xmt_excessive_collision   0x2D
#define xmt_back_pressure   0x2E
#define xmt_flow_ctrl   0x2F
#define xmt_pkts_64_octets   0x30
#define xmt_pkts_65to127_octets   0x31
#define xmt_pkts_128to255_octets   0x32
#define xmt_pkts_256to511_octets   0x33
#define xmt_pkts_512to1023_octets   0x34
#define xmt_pkts_1024to1518_octet   0x35
#define xmt_oversize_pkts   0x36
#define xmt_jumbo_pkts   0x37
#define DEFAULT_IPG   0x60
#define IFS1_DELTA   36
#define IPG_CONVERGE_JIFFIES   (HZ/2)
#define IPG_STABLE_TIME   5
#define MIN_IPG   96
#define MAX_IPG   255
#define IPG_STEP   16
#define CSTATE   1
#define SSTATE   2
#define RESET_RX_FLAGS   0x0000
#define TT_MASK   0x000c
#define TCC_MASK   0x0003
#define AMD8111E_REG_DUMP_LEN   13*sizeof(u32)
#define CRC32   0xedb88320
#define INITCRC   0xFFFFFFFF
#define amd8111e_writeq(_UlData, _memMap)

Enumerations

enum  STAT_ASF_BITS { ASF_INIT_DONE = (1 << 1), ASF_INIT_PRESENT = (1 << 0) }
enum  MIB_ADDR_BITS { MIB_CMD_ACTIVE = (1 << 15 ), MIB_RD_CMD = (1 << 13 ), MIB_CLEAR = (1 << 12 ), MIB_ADDRESS }
enum  STAT0_BITS {
  PMAT_DET = (1 << 12), MP_DET = (1 << 11), LC_DET = (1 << 10), SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),
  FULL_DPLX = (1 << 6), LINK_STATS = (1 << 5), AUTONEG_COMPLETE = (1 << 4), MIIPD = (1 << 3),
  RX_SUSPENDED = (1 << 2), TX_SUSPENDED = (1 << 1), RUNNING = (1 << 0)
}
enum  INT0_BITS {
  INTR = (1 << 31), PCSINT = (1 << 28), LCINT = (1 << 27), APINT5 = (1 << 26),
  APINT4 = (1 << 25), APINT3 = (1 << 24), TINT_SUM = (1 << 23), APINT2 = (1 << 22),
  APINT1 = (1 << 21), APINT0 = (1 << 20), MIIPDTINT = (1 << 19), MCCINT = (1 << 17),
  MREINT = (1 << 16), RINT_SUM = (1 << 15), SPNDINT = (1 << 14), MPINT = (1 << 13),
  SINT = (1 << 12), TINT3 = (1 << 11), TINT2 = (1 << 10), TINT1 = (1 << 9),
  TINT0 = (1 << 8), UINT = (1 << 7), STINT = (1 << 4), RINT0 = (1 << 0)
}
enum  VAL_BITS { VAL3 = (1 << 31), VAL2 = (1 << 23), VAL1 = (1 << 15), VAL0 = (1 << 7) }
enum  INTEN0_BITS {
  LCINTEN = (1 << 27), APINT5EN = (1 << 26), APINT4EN = (1 << 25), APINT3EN = (1 << 24),
  APINT2EN = (1 << 22), APINT1EN = (1 << 21), APINT0EN = (1 << 20), MIIPDTINTEN = (1 << 19),
  MCCIINTEN = (1 << 18), MCCINTEN = (1 << 17), MREINTEN = (1 << 16), SPNDINTEN = (1 << 14),
  MPINTEN = (1 << 13), TINTEN3 = (1 << 11), SINTEN = (1 << 12), TINTEN2 = (1 << 10),
  TINTEN1 = (1 << 9), TINTEN0 = (1 << 8), STINTEN = (1 << 4), RINTEN0 = (1 << 0),
  INTEN0_CLEAR = 0x1F7F7F1F
}
enum  CMD0_BITS {
  RDMD0 = (1 << 16), TDMD3 = (1 << 11), TDMD2 = (1 << 10), TDMD1 = (1 << 9),
  TDMD0 = (1 << 8), UINTCMD = (1 << 6), RX_FAST_SPND = (1 << 5), TX_FAST_SPND = (1 << 4),
  RX_SPND = (1 << 3), TX_SPND = (1 << 2), INTREN = (1 << 1), RUN = (1 << 0),
  CMD0_CLEAR = 0x000F0F7F
}
enum  CMD2_BITS {
  CONDUIT_MODE = (1 << 29), RPA = (1 << 19), DRCVPA = (1 << 18), DRCVBC = (1 << 17),
  PROM = (1 << 16), ASTRP_RCV = (1 << 13), RCV_DROP0 = (1 << 12), EMBA = (1 << 11),
  DXMT2PD = (1 << 10), LTINTEN = (1 << 9), DXMTFCS = (1 << 8), APAD_XMT = (1 << 6),
  DRTY = (1 << 5), INLOOP = (1 << 4), EXLOOP = (1 << 3), REX_RTRY = (1 << 2),
  REX_UFLO = (1 << 1), REX_LCOL = (1 << 0), CMD2_CLEAR = 0x3F7F3F7F
}
enum  CMD3_BITS {
  ASF_INIT_DONE_ALIAS = (1 << 29), JUMBO = (1 << 21), VSIZE = (1 << 20), VLONLY = (1 << 19),
  VL_TAG_DEL = (1 << 18), EN_PMGR = (1 << 14), INTLEVEL = (1 << 13), FORCE_FULL_DUPLEX = (1 << 12),
  FORCE_LINK_STATUS = (1 << 11), APEP = (1 << 10), MPPLBA = (1 << 9), RESET_PHY_PULSE = (1 << 2),
  RESET_PHY = (1 << 1), PHY_RST_POL = (1 << 0)
}
enum  CMD7_BITS {
  PMAT_SAVE_MATCH = (1 << 4), PMAT_MODE = (1 << 3), MPEN_SW = (1 << 1), LCMODE_SW = (1 << 0),
  CMD7_CLEAR = 0x0000001B
}
enum  CTRL1_BITS {
  RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), XMTSP_MASK = (1 << 9) | (1 << 8), XMTSP_128 = (1 << 9), XMTSP_64 = (1 << 8),
  CACHE_ALIGN = (1 << 4), BURST_LIMIT_MASK = (0xF << 0 ), CTRL1_DEFAULT = 0x00010111
}
enum  CTRL2_BITS {
  FMDC_MASK = (1 << 9)|(1 << 8), XPHYRST = (1 << 7), XPHYANE = (1 << 6), XPHYFD = (1 << 5),
  XPHYSP = (1 << 4) | (1 << 3), APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0)
}
enum  XMT_RING_LIMIT_BITS { XMT_RING2_LIMIT = (0xFF << 16), XMT_RING1_LIMIT = (0xFF << 8), XMT_RING0_LIMIT = (0xFF << 0) }
enum  AUTOPOLL0_BITS { AP_REG0_EN = (1 << 15), AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4) }
enum  AUTOPOLL1_BITS {
  AP_REG1_EN = (1 << 15), AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP1 = (1 << 6), AP_PHY1_DFLT = (1 << 5),
  AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL2_BITS {
  AP_REG2_EN = (1 << 15), AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP2 = (1 << 6), AP_PHY2_DFLT = (1 << 5),
  AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL3_BITS {
  AP_REG3_EN = (1 << 15), AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP3 = (1 << 6), AP_PHY3_DFLT = (1 << 5),
  AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL4_BITS {
  AP_REG4_EN = (1 << 15), AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP4 = (1 << 6), AP_PHY4_DFLT = (1 << 5),
  AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AUTOPOLL5_BITS {
  AP_REG5_EN = (1 << 15), AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP5 = (1 << 6), AP_PHY5_DFLT = (1 << 5),
  AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4)
}
enum  AP_VALUE_BITS { AP_VAL_ACTIVE = (1 << 31), AP_VAL_RD_CMD = ( 1 << 29), AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), AP_VAL }
enum  DLY_INT_A_BITS {
  DLY_INT_A_R3 = (1 << 31), DLY_INT_A_R2 = (1 << 30), DLY_INT_A_R1 = (1 << 29), DLY_INT_A_R0 = (1 << 28),
  DLY_INT_A_T3 = (1 << 27), DLY_INT_A_T2 = (1 << 26), DLY_INT_A_T1 = (1 << 25), DLY_INT_A_T0 = ( 1 << 24),
  EVENT_COUNT_A = (0xF << 16) | (0x1 << 20), MAX_DELAY_TIME_A
}
enum  DLY_INT_B_BITS {
  DLY_INT_B_R3 = (1 << 31), DLY_INT_B_R2 = (1 << 30), DLY_INT_B_R1 = (1 << 29), DLY_INT_B_R0 = (1 << 28),
  DLY_INT_B_T3 = (1 << 27), DLY_INT_B_T2 = (1 << 26), DLY_INT_B_T1 = (1 << 25), DLY_INT_B_T0 = ( 1 << 24),
  EVENT_COUNT_B = (0xF << 16) | (0x1 << 20), MAX_DELAY_TIME_B
}
enum  FLOW_CONTROL_BITS {
  PAUSE_LEN_CHG = (1 << 30), FTPE = (1 << 22), FRPE = (1 << 21), NAPA = (1 << 20),
  NPA = (1 << 19), FIXP = ( 1 << 18), FCCMD = ( 1 << 16), PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12)
}
enum  PHY_ACCESS_BITS {
  PHY_CMD_ACTIVE = (1 << 31), PHY_WR_CMD = (1 << 30), PHY_RD_CMD = (1 << 29), PHY_RD_ERR = (1 << 28),
  PHY_PRE_SUP = (1 << 27), PHY_ADDR, PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20), PHY_DATA
}
enum  PMAT0_BITS {
  PMR_ACTIVE = (1 << 31), PMR_WR_CMD = (1 << 30), PMR_RD_CMD = (1 << 29), PMR_BANK = (1 <<28),
  PMR_ADDR, PMR_B4 = (0xF << 0) | (0xF << 4)
}
enum  PMAT1_BITS { PMR_B3 = (0xF << 24) | (0xF <<28), PMR_B2 = (0xF << 16) |(0xF << 20), PMR_B1 = (0xF << 8) | (0xF <<12), PMR_B0 = (0xF << 0)|(0xF << 4) }
enum  TX_FLAG_BITS {
  OWN_BIT = (1 << 15), ADD_FCS_BIT = (1 << 13), LTINT_BIT = (1 << 12), STP_BIT = (1 << 9),
  ENP_BIT = (1 << 8), KILL_BIT = (1 << 6), TCC_VLAN_INSERT = (1 << 1), TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0)
}
enum  RX_FLAG_BITS {
  ERR_BIT = (1 << 14), FRAM_BIT = (1 << 13), OFLO_BIT = (1 << 12), CRC_BIT = (1 << 11),
  PAM_BIT = (1 << 6), LAFM_BIT = (1 << 5), BAM_BIT = (1 << 4), TT_VLAN_TAGGED = (1 << 3) |(1 << 2),
  TT_PRTY_TAGGED = (1 << 3)
}
enum  EXT_PHY_OPTION {
  SPEED_AUTONEG, SPEED10_HALF, SPEED10_FULL, SPEED100_HALF,
  SPEED100_FULL
}

Functions

 FILE_LICENCE (GPL2_OR_LATER)

Define Documentation

#define ASF_STAT   0x00

Definition at line 54 of file amd8111e.h.

#define CHIPID   0x04

Definition at line 55 of file amd8111e.h.

#define MIB_DATA   0x10

Definition at line 56 of file amd8111e.h.

#define MIB_ADDR   0x14

Definition at line 57 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define STAT0   0x30

Definition at line 58 of file amd8111e.h.

Referenced by amd8111e_poll_link(), and amd8111e_wait_link().

#define INT0   0x38

Definition at line 59 of file amd8111e.h.

Referenced by amd8111e_disable_interrupt(), and amd8111e_init_hw_default().

#define INTEN0   0x40

Definition at line 60 of file amd8111e.h.

Referenced by amd8111e_disable_interrupt(), amd8111e_enable_interrupt(), and amd8111e_init_hw_default().

#define CMD0   0x48

Definition at line 61 of file amd8111e.h.

Referenced by amd8111e_disable_interrupt(), amd8111e_enable_interrupt(), amd8111e_force_interrupt(), amd8111e_init_hw_default(), amd8111e_poll(), amd8111e_start(), and amd8111e_transmit().

#define CMD2   0x50

Definition at line 62 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

#define CMD3   0x54

Definition at line 63 of file amd8111e.h.

Referenced by amd8111e_start().

#define CMD7   0x64

Definition at line 64 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define CTRL1   0x6C

Definition at line 66 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

#define CTRL2   0x70

Definition at line 67 of file amd8111e.h.

Referenced by amd8111e_start().

#define XMT_RING_LIMIT   0x7C

Definition at line 69 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define AUTOPOLL0   0x88

Definition at line 71 of file amd8111e.h.

Referenced by amd8111e_start().

#define AUTOPOLL1   0x8A

Definition at line 72 of file amd8111e.h.

#define AUTOPOLL2   0x8C

Definition at line 73 of file amd8111e.h.

#define AUTOPOLL3   0x8E

Definition at line 74 of file amd8111e.h.

#define AUTOPOLL4   0x90

Definition at line 75 of file amd8111e.h.

#define AUTOPOLL5   0x92

Definition at line 76 of file amd8111e.h.

#define AP_VALUE   0x98

Definition at line 78 of file amd8111e.h.

#define DLY_INT_A   0xA8

Definition at line 79 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define DLY_INT_B   0xAC

Definition at line 80 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define FLOW_CONTROL   0xC8

Definition at line 82 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define PHY_ACCESS   0xD0

Definition at line 83 of file amd8111e.h.

Referenced by amd8111e_read_phy().

#define STVAL   0xD8

Definition at line 85 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define XMT_RING_BASE_ADDR0   0x100

Definition at line 87 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

#define XMT_RING_BASE_ADDR1   0x108

Definition at line 88 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define XMT_RING_BASE_ADDR2   0x110

Definition at line 89 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define XMT_RING_BASE_ADDR3   0x118

Definition at line 90 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define RCV_RING_BASE_ADDR0   0x120

Definition at line 92 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

#define PMAT0   0x190

Definition at line 94 of file amd8111e.h.

#define PMAT1   0x194

Definition at line 95 of file amd8111e.h.

#define XMT_RING_LEN0   0x140

Definition at line 99 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

#define XMT_RING_LEN1   0x144

Definition at line 100 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define XMT_RING_LEN2   0x148

Definition at line 101 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define XMT_RING_LEN3   0x14C

Definition at line 102 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define RCV_RING_LEN0   0x150

Definition at line 104 of file amd8111e.h.

Referenced by amd8111e_init_hw_default(), and amd8111e_start().

#define SRAM_SIZE   0x178

Definition at line 106 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define SRAM_BOUNDARY   0x17A

Definition at line 107 of file amd8111e.h.

#define PADR   0x160

Definition at line 111 of file amd8111e.h.

Referenced by amd8111e_get_mac_address(), and amd8111e_start().

#define IFS1   0x18C

Definition at line 113 of file amd8111e.h.

Referenced by amd8111e_start().

#define IFS   0x18D

Definition at line 114 of file amd8111e.h.

#define IPG   0x18E

Definition at line 115 of file amd8111e.h.

Referenced by amd8111e_start().

#define LADRF   0x168

Definition at line 118 of file amd8111e.h.

Referenced by amd8111e_init_hw_default().

#define PHY_SPEED_10   0x2

Definition at line 155 of file amd8111e.h.

#define PHY_SPEED_100   0x3

Definition at line 156 of file amd8111e.h.

Referenced by amd8111e_poll_link().

#define rcv_miss_pkts   0x00

Definition at line 512 of file amd8111e.h.

#define rcv_octets   0x01

Definition at line 513 of file amd8111e.h.

#define rcv_broadcast_pkts   0x02

Definition at line 514 of file amd8111e.h.

#define rcv_multicast_pkts   0x03

Definition at line 515 of file amd8111e.h.

#define rcv_undersize_pkts   0x04

Definition at line 516 of file amd8111e.h.

#define rcv_oversize_pkts   0x05

Definition at line 517 of file amd8111e.h.

#define rcv_fragments   0x06

Definition at line 518 of file amd8111e.h.

#define rcv_jabbers   0x07

Definition at line 519 of file amd8111e.h.

#define rcv_unicast_pkts   0x08

Definition at line 520 of file amd8111e.h.

#define rcv_alignment_errors   0x09

Definition at line 521 of file amd8111e.h.

#define rcv_fcs_errors   0x0A

Definition at line 522 of file amd8111e.h.

#define rcv_good_octets   0x0B

Definition at line 523 of file amd8111e.h.

#define rcv_mac_ctrl   0x0C

Definition at line 524 of file amd8111e.h.

#define rcv_flow_ctrl   0x0D

Definition at line 525 of file amd8111e.h.

#define rcv_pkts_64_octets   0x0E

Definition at line 526 of file amd8111e.h.

#define rcv_pkts_65to127_octets   0x0F

Definition at line 527 of file amd8111e.h.

#define rcv_pkts_128to255_octets   0x10

Definition at line 528 of file amd8111e.h.

#define rcv_pkts_256to511_octets   0x11

Definition at line 529 of file amd8111e.h.

#define rcv_pkts_512to1023_octets   0x12

Definition at line 530 of file amd8111e.h.

#define rcv_pkts_1024to1518_octets   0x13

Definition at line 531 of file amd8111e.h.

#define rcv_unsupported_opcode   0x14

Definition at line 532 of file amd8111e.h.

#define rcv_symbol_errors   0x15

Definition at line 533 of file amd8111e.h.

#define rcv_drop_pkts_ring1   0x16

Definition at line 534 of file amd8111e.h.

#define rcv_drop_pkts_ring2   0x17

Definition at line 535 of file amd8111e.h.

#define rcv_drop_pkts_ring3   0x18

Definition at line 536 of file amd8111e.h.

#define rcv_drop_pkts_ring4   0x19

Definition at line 537 of file amd8111e.h.

#define rcv_jumbo_pkts   0x1A

Definition at line 538 of file amd8111e.h.

#define xmt_underrun_pkts   0x20

Definition at line 540 of file amd8111e.h.

#define xmt_octets   0x21

Definition at line 541 of file amd8111e.h.

#define xmt_packets   0x22

Definition at line 542 of file amd8111e.h.

#define xmt_broadcast_pkts   0x23

Definition at line 543 of file amd8111e.h.

#define xmt_multicast_pkts   0x24

Definition at line 544 of file amd8111e.h.

#define xmt_collisions   0x25

Definition at line 545 of file amd8111e.h.

#define xmt_unicast_pkts   0x26

Definition at line 546 of file amd8111e.h.

#define xmt_one_collision   0x27

Definition at line 547 of file amd8111e.h.

#define xmt_multiple_collision   0x28

Definition at line 548 of file amd8111e.h.

#define xmt_deferred_transmit   0x29

Definition at line 549 of file amd8111e.h.

#define xmt_late_collision   0x2A

Definition at line 550 of file amd8111e.h.

#define xmt_excessive_defer   0x2B

Definition at line 551 of file amd8111e.h.

#define xmt_loss_carrier   0x2C

Definition at line 552 of file amd8111e.h.

#define xmt_excessive_collision   0x2D

Definition at line 553 of file amd8111e.h.

#define xmt_back_pressure   0x2E

Definition at line 554 of file amd8111e.h.

#define xmt_flow_ctrl   0x2F

Definition at line 555 of file amd8111e.h.

#define xmt_pkts_64_octets   0x30

Definition at line 556 of file amd8111e.h.

#define xmt_pkts_65to127_octets   0x31

Definition at line 557 of file amd8111e.h.

#define xmt_pkts_128to255_octets   0x32

Definition at line 558 of file amd8111e.h.

#define xmt_pkts_256to511_octets   0x33

Definition at line 559 of file amd8111e.h.

#define xmt_pkts_512to1023_octets   0x34

Definition at line 560 of file amd8111e.h.

#define xmt_pkts_1024to1518_octet   0x35

Definition at line 561 of file amd8111e.h.

#define xmt_oversize_pkts   0x36

Definition at line 562 of file amd8111e.h.

#define xmt_jumbo_pkts   0x37

Definition at line 563 of file amd8111e.h.

#define DEFAULT_IPG   0x60

Definition at line 566 of file amd8111e.h.

Referenced by amd8111e_start().

#define IFS1_DELTA   36

Definition at line 567 of file amd8111e.h.

Referenced by amd8111e_start().

#define IPG_CONVERGE_JIFFIES   (HZ/2)

Definition at line 568 of file amd8111e.h.

#define IPG_STABLE_TIME   5

Definition at line 569 of file amd8111e.h.

#define MIN_IPG   96

Definition at line 570 of file amd8111e.h.

#define MAX_IPG   255

Definition at line 571 of file amd8111e.h.

#define IPG_STEP   16

Definition at line 572 of file amd8111e.h.

#define CSTATE   1

Definition at line 573 of file amd8111e.h.

#define SSTATE   2

Definition at line 574 of file amd8111e.h.

#define RESET_RX_FLAGS   0x0000

Definition at line 603 of file amd8111e.h.

#define TT_MASK   0x000c

Definition at line 604 of file amd8111e.h.

#define TCC_MASK   0x0003

Definition at line 605 of file amd8111e.h.

#define AMD8111E_REG_DUMP_LEN   13*sizeof(u32)

Definition at line 608 of file amd8111e.h.

#define CRC32   0xedb88320

Definition at line 611 of file amd8111e.h.

#define INITCRC   0xFFFFFFFF

Definition at line 612 of file amd8111e.h.

#define amd8111e_writeq ( _UlData,
_memMap   ) 

Value:

writel(*(u32*)(&_UlData), _memMap);     \
                writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)

Definition at line 616 of file amd8111e.h.

Enumeration Type Documentation

enum STAT_ASF_BITS

Enumerator:
ASF_INIT_DONE 
ASF_INIT_PRESENT 

Definition at line 122 of file amd8111e.h.

00122              {
00123 
00124         ASF_INIT_DONE           = (1 << 1),
00125         ASF_INIT_PRESENT        = (1 << 0),
00126 
00127 }STAT_ASF_BITS;

enum MIB_ADDR_BITS

Enumerator:
MIB_CMD_ACTIVE 
MIB_RD_CMD 
MIB_CLEAR 
MIB_ADDRESS 

Definition at line 129 of file amd8111e.h.

00129              {
00130 
00131         MIB_CMD_ACTIVE          = (1 << 15 ),
00132         MIB_RD_CMD              = (1 << 13 ),
00133         MIB_CLEAR               = (1 << 12 ),
00134         MIB_ADDRESS             = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
00135                                         (1 << 4) | (1 << 5),
00136 }MIB_ADDR_BITS;

enum STAT0_BITS

Enumerator:
PMAT_DET 
MP_DET 
LC_DET 
SPEED_MASK 
FULL_DPLX 
LINK_STATS 
AUTONEG_COMPLETE 
MIIPD 
RX_SUSPENDED 
TX_SUSPENDED 
RUNNING 

Definition at line 139 of file amd8111e.h.

00139              {
00140         
00141         PMAT_DET                = (1 << 12),
00142         MP_DET                  = (1 << 11),
00143         LC_DET                  = (1 << 10),
00144         SPEED_MASK              = (1 << 9)|(1 << 8)|(1 << 7),
00145         FULL_DPLX               = (1 << 6),
00146         LINK_STATS              = (1 << 5),
00147         AUTONEG_COMPLETE        = (1 << 4),
00148         MIIPD                   = (1 << 3),
00149         RX_SUSPENDED            = (1 << 2),
00150         TX_SUSPENDED            = (1 << 1),
00151         RUNNING                 = (1 << 0),
00152 
00153 }STAT0_BITS;

enum INT0_BITS

Enumerator:
INTR 
PCSINT 
LCINT 
APINT5 
APINT4 
APINT3 
TINT_SUM 
APINT2 
APINT1 
APINT0 
MIIPDTINT 
MCCINT 
MREINT 
RINT_SUM 
SPNDINT 
MPINT 
SINT 
TINT3 
TINT2 
TINT1 
TINT0 
UINT 
STINT 
RINT0 

Definition at line 159 of file amd8111e.h.

00159              {
00160 
00161         INTR                    = (1 << 31),
00162         PCSINT                  = (1 << 28), 
00163         LCINT                   = (1 << 27),
00164         APINT5                  = (1 << 26),
00165         APINT4                  = (1 << 25),
00166         APINT3                  = (1 << 24),
00167         TINT_SUM                = (1 << 23),
00168         APINT2                  = (1 << 22),
00169         APINT1                  = (1 << 21),
00170         APINT0                  = (1 << 20),
00171         MIIPDTINT               = (1 << 19),
00172         MCCINT                  = (1 << 17),
00173         MREINT                  = (1 << 16),
00174         RINT_SUM                = (1 << 15),
00175         SPNDINT                 = (1 << 14),
00176         MPINT                   = (1 << 13),
00177         SINT                    = (1 << 12),
00178         TINT3                   = (1 << 11),
00179         TINT2                   = (1 << 10),
00180         TINT1                   = (1 << 9),
00181         TINT0                   = (1 << 8),
00182         UINT                    = (1 << 7),
00183         STINT                   = (1 << 4),
00184         RINT0                   = (1 << 0),
00185 
00186 }INT0_BITS;

enum VAL_BITS

Enumerator:
VAL3 
VAL2 
VAL1 
VAL0 

Definition at line 188 of file amd8111e.h.

00188              {
00189 
00190         VAL3                    = (1 << 31),   /* VAL bit for byte 3 */
00191         VAL2                    = (1 << 23),   /* VAL bit for byte 2 */
00192         VAL1                    = (1 << 15),   /* VAL bit for byte 1 */
00193         VAL0                    = (1 << 7),    /* VAL bit for byte 0 */
00194 
00195 }VAL_BITS;

enum INTEN0_BITS

Enumerator:
LCINTEN 
APINT5EN 
APINT4EN 
APINT3EN 
APINT2EN 
APINT1EN 
APINT0EN 
MIIPDTINTEN 
MCCIINTEN 
MCCINTEN 
MREINTEN 
SPNDINTEN 
MPINTEN 
TINTEN3 
SINTEN 
TINTEN2 
TINTEN1 
TINTEN0 
STINTEN 
RINTEN0 
INTEN0_CLEAR 

Definition at line 197 of file amd8111e.h.

00197              {
00198 
00199         /* VAL3 */
00200         LCINTEN                 = (1 << 27),
00201         APINT5EN                = (1 << 26),
00202         APINT4EN                = (1 << 25),
00203         APINT3EN                = (1 << 24),
00204         /* VAL2 */
00205         APINT2EN                = (1 << 22),
00206         APINT1EN                = (1 << 21),
00207         APINT0EN                = (1 << 20),
00208         MIIPDTINTEN             = (1 << 19),
00209         MCCIINTEN               = (1 << 18),
00210         MCCINTEN                = (1 << 17),
00211         MREINTEN                = (1 << 16),
00212         /* VAL1 */
00213         SPNDINTEN               = (1 << 14),
00214         MPINTEN                 = (1 << 13),
00215         TINTEN3                 = (1 << 11),
00216         SINTEN                  = (1 << 12),
00217         TINTEN2                 = (1 << 10),
00218         TINTEN1                 = (1 << 9),
00219         TINTEN0                 = (1 << 8),
00220         /* VAL0 */
00221         STINTEN                 = (1 << 4),
00222         RINTEN0                 = (1 << 0),
00223 
00224         INTEN0_CLEAR            = 0x1F7F7F1F, /* Command style register */
00225 
00226 }INTEN0_BITS;

enum CMD0_BITS

Enumerator:
RDMD0 
TDMD3 
TDMD2 
TDMD1 
TDMD0 
UINTCMD 
RX_FAST_SPND 
TX_FAST_SPND 
RX_SPND 
TX_SPND 
INTREN 
RUN 
CMD0_CLEAR 

Definition at line 228 of file amd8111e.h.

00228              {
00229         /* VAL2 */
00230         RDMD0                   = (1 << 16),
00231         /* VAL1 */
00232         TDMD3                   = (1 << 11),
00233         TDMD2                   = (1 << 10),
00234         TDMD1                   = (1 << 9),
00235         TDMD0                   = (1 << 8),
00236         /* VAL0 */
00237         UINTCMD                 = (1 << 6),
00238         RX_FAST_SPND            = (1 << 5),
00239         TX_FAST_SPND            = (1 << 4),
00240         RX_SPND                 = (1 << 3),
00241         TX_SPND                 = (1 << 2),
00242         INTREN                  = (1 << 1),
00243         RUN                     = (1 << 0),
00244 
00245         CMD0_CLEAR              = 0x000F0F7F,   /* Command style register */    
00246 
00247 }CMD0_BITS;

enum CMD2_BITS

Enumerator:
CONDUIT_MODE 
RPA 
DRCVPA 
DRCVBC 
PROM 
ASTRP_RCV 
RCV_DROP0 
EMBA 
DXMT2PD 
LTINTEN 
DXMTFCS 
APAD_XMT 
DRTY 
INLOOP 
EXLOOP 
REX_RTRY 
REX_UFLO 
REX_LCOL 
CMD2_CLEAR 

Definition at line 249 of file amd8111e.h.

00249              {
00250 
00251         /* VAL3 */
00252         CONDUIT_MODE            = (1 << 29),
00253         /* VAL2 */
00254         RPA                     = (1 << 19),
00255         DRCVPA                  = (1 << 18),
00256         DRCVBC                  = (1 << 17),
00257         PROM                    = (1 << 16),
00258         /* VAL1 */
00259         ASTRP_RCV               = (1 << 13),
00260         RCV_DROP0               = (1 << 12),
00261         EMBA                    = (1 << 11),
00262         DXMT2PD                 = (1 << 10),
00263         LTINTEN                 = (1 << 9),
00264         DXMTFCS                 = (1 << 8),
00265         /* VAL0 */
00266         APAD_XMT                = (1 << 6),
00267         DRTY                    = (1 << 5),
00268         INLOOP                  = (1 << 4),
00269         EXLOOP                  = (1 << 3),
00270         REX_RTRY                = (1 << 2),
00271         REX_UFLO                = (1 << 1),
00272         REX_LCOL                = (1 << 0),
00273 
00274         CMD2_CLEAR              = 0x3F7F3F7F,   /* Command style register */
00275 
00276 }CMD2_BITS;

enum CMD3_BITS

Enumerator:
ASF_INIT_DONE_ALIAS 
JUMBO 
VSIZE 
VLONLY 
VL_TAG_DEL 
EN_PMGR 
INTLEVEL 
FORCE_FULL_DUPLEX 
FORCE_LINK_STATUS 
APEP 
MPPLBA 
RESET_PHY_PULSE 
RESET_PHY 
PHY_RST_POL 

Definition at line 278 of file amd8111e.h.

00278              {
00279 
00280         /* VAL3 */
00281         ASF_INIT_DONE_ALIAS     = (1 << 29),
00282         /* VAL2 */
00283         JUMBO                   = (1 << 21),
00284         VSIZE                   = (1 << 20),    
00285         VLONLY                  = (1 << 19),
00286         VL_TAG_DEL              = (1 << 18),    
00287         /* VAL1 */
00288         EN_PMGR                 = (1 << 14),                    
00289         INTLEVEL                = (1 << 13),
00290         FORCE_FULL_DUPLEX       = (1 << 12),    
00291         FORCE_LINK_STATUS       = (1 << 11),    
00292         APEP                    = (1 << 10),    
00293         MPPLBA                  = (1 << 9),     
00294         /* VAL0 */
00295         RESET_PHY_PULSE         = (1 << 2),     
00296         RESET_PHY               = (1 << 1),     
00297         PHY_RST_POL             = (1 << 0),     
00298 
00299 }CMD3_BITS;

enum CMD7_BITS

Enumerator:
PMAT_SAVE_MATCH 
PMAT_MODE 
MPEN_SW 
LCMODE_SW 
CMD7_CLEAR 

Definition at line 302 of file amd8111e.h.

00302              {
00303 
00304         /* VAL0 */
00305         PMAT_SAVE_MATCH         = (1 << 4),
00306         PMAT_MODE               = (1 << 3),
00307         MPEN_SW                 = (1 << 1),
00308         LCMODE_SW               = (1 << 0),
00309 
00310         CMD7_CLEAR              = 0x0000001B    /* Command style register */
00311 
00312 }CMD7_BITS;

enum CTRL1_BITS

Enumerator:
RESET_PHY_WIDTH 
XMTSP_MASK 
XMTSP_128 
XMTSP_64 
CACHE_ALIGN 
BURST_LIMIT_MASK 
CTRL1_DEFAULT 

Definition at line 315 of file amd8111e.h.

00315              {
00316 
00317         RESET_PHY_WIDTH         = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
00318         XMTSP_MASK              = (1 << 9) | (1 << 8),  /* 9:8 */
00319         XMTSP_128               = (1 << 9),     /* 9 */ 
00320         XMTSP_64                = (1 << 8),
00321         CACHE_ALIGN             = (1 << 4),
00322         BURST_LIMIT_MASK        = (0xF << 0 ),
00323         CTRL1_DEFAULT           = 0x00010111,
00324 
00325 }CTRL1_BITS;

enum CTRL2_BITS

Enumerator:
FMDC_MASK 
XPHYRST 
XPHYANE 
XPHYFD 
XPHYSP 
APDW_MASK 

Definition at line 327 of file amd8111e.h.

00327              {
00328 
00329         FMDC_MASK               = (1 << 9)|(1 << 8),    /* 9:8 */
00330         XPHYRST                 = (1 << 7),
00331         XPHYANE                 = (1 << 6),
00332         XPHYFD                  = (1 << 5),
00333         XPHYSP                  = (1 << 4) | (1 << 3),  /* 4:3 */
00334         APDW_MASK               = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
00335 
00336 }CTRL2_BITS;

enum XMT_RING_LIMIT_BITS

Enumerator:
XMT_RING2_LIMIT 
XMT_RING1_LIMIT 
XMT_RING0_LIMIT 

Definition at line 339 of file amd8111e.h.

00339              {
00340 
00341         XMT_RING2_LIMIT         = (0xFF << 16), /* 23:16 */
00342         XMT_RING1_LIMIT         = (0xFF << 8),  /* 15:8 */
00343         XMT_RING0_LIMIT         = (0xFF << 0),  /* 7:0 */
00344 
00345 }XMT_RING_LIMIT_BITS;

enum AUTOPOLL0_BITS

Enumerator:
AP_REG0_EN 
AP_REG0_ADDR_MASK 
AP_PHY0_ADDR_MASK 

Definition at line 347 of file amd8111e.h.

00347              {
00348 
00349         AP_REG0_EN              = (1 << 15),
00350         AP_REG0_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00351         AP_PHY0_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00352 
00353 }AUTOPOLL0_BITS;

enum AUTOPOLL1_BITS

Enumerator:
AP_REG1_EN 
AP_REG1_ADDR_MASK 
AP_PRE_SUP1 
AP_PHY1_DFLT 
AP_PHY1_ADDR_MASK 

Definition at line 356 of file amd8111e.h.

00356              {
00357 
00358         AP_REG1_EN              = (1 << 15),
00359         AP_REG1_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00360         AP_PRE_SUP1             = (1 << 6),
00361         AP_PHY1_DFLT            = (1 << 5),
00362         AP_PHY1_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00363 
00364 }AUTOPOLL1_BITS;

enum AUTOPOLL2_BITS

Enumerator:
AP_REG2_EN 
AP_REG2_ADDR_MASK 
AP_PRE_SUP2 
AP_PHY2_DFLT 
AP_PHY2_ADDR_MASK 

Definition at line 367 of file amd8111e.h.

00367              {
00368 
00369         AP_REG2_EN              = (1 << 15),
00370         AP_REG2_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00371         AP_PRE_SUP2             = (1 << 6),
00372         AP_PHY2_DFLT            = (1 << 5),
00373         AP_PHY2_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00374 
00375 }AUTOPOLL2_BITS;

enum AUTOPOLL3_BITS

Enumerator:
AP_REG3_EN 
AP_REG3_ADDR_MASK 
AP_PRE_SUP3 
AP_PHY3_DFLT 
AP_PHY3_ADDR_MASK 

Definition at line 377 of file amd8111e.h.

00377              {
00378 
00379         AP_REG3_EN              = (1 << 15),
00380         AP_REG3_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00381         AP_PRE_SUP3             = (1 << 6),
00382         AP_PHY3_DFLT            = (1 << 5),
00383         AP_PHY3_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00384 
00385 }AUTOPOLL3_BITS;

enum AUTOPOLL4_BITS

Enumerator:
AP_REG4_EN 
AP_REG4_ADDR_MASK 
AP_PRE_SUP4 
AP_PHY4_DFLT 
AP_PHY4_ADDR_MASK 

Definition at line 388 of file amd8111e.h.

00388              {
00389 
00390         AP_REG4_EN              = (1 << 15),
00391         AP_REG4_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00392         AP_PRE_SUP4             = (1 << 6),
00393         AP_PHY4_DFLT            = (1 << 5),
00394         AP_PHY4_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00395 
00396 }AUTOPOLL4_BITS;

enum AUTOPOLL5_BITS

Enumerator:
AP_REG5_EN 
AP_REG5_ADDR_MASK 
AP_PRE_SUP5 
AP_PHY5_DFLT 
AP_PHY5_ADDR_MASK 

Definition at line 399 of file amd8111e.h.

00399              {
00400 
00401         AP_REG5_EN              = (1 << 15),
00402         AP_REG5_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
00403         AP_PRE_SUP5             = (1 << 6),
00404         AP_PHY5_DFLT            = (1 << 5),
00405         AP_PHY5_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
00406 
00407 }AUTOPOLL5_BITS;

enum AP_VALUE_BITS

Enumerator:
AP_VAL_ACTIVE 
AP_VAL_RD_CMD 
AP_ADDR 
AP_VAL 

Definition at line 413 of file amd8111e.h.

00413              {
00414 
00415         AP_VAL_ACTIVE           = (1 << 31),
00416         AP_VAL_RD_CMD           = ( 1 << 29),
00417         AP_ADDR                 = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
00418         AP_VAL                  = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
00419                                   (0xF << 12),  /* 15:0 */
00420 
00421 }AP_VALUE_BITS;

enum DLY_INT_A_BITS

Enumerator:
DLY_INT_A_R3 
DLY_INT_A_R2 
DLY_INT_A_R1 
DLY_INT_A_R0 
DLY_INT_A_T3 
DLY_INT_A_T2 
DLY_INT_A_T1 
DLY_INT_A_T0 
EVENT_COUNT_A 
MAX_DELAY_TIME_A 

Definition at line 423 of file amd8111e.h.

00423              {
00424 
00425         DLY_INT_A_R3            = (1 << 31),
00426         DLY_INT_A_R2            = (1 << 30),
00427         DLY_INT_A_R1            = (1 << 29),
00428         DLY_INT_A_R0            = (1 << 28),
00429         DLY_INT_A_T3            = (1 << 27),
00430         DLY_INT_A_T2            = (1 << 26),
00431         DLY_INT_A_T1            = (1 << 25),
00432         DLY_INT_A_T0            = ( 1 << 24),
00433         EVENT_COUNT_A           = (0xF << 16) | (0x1 << 20),/* 20:16 */
00434         MAX_DELAY_TIME_A        = (0xF << 0) | (0xF << 4) | (1 << 8)|
00435                                   (1 << 9) | (1 << 10), /* 10:0 */
00436 
00437 }DLY_INT_A_BITS;

enum DLY_INT_B_BITS

Enumerator:
DLY_INT_B_R3 
DLY_INT_B_R2 
DLY_INT_B_R1 
DLY_INT_B_R0 
DLY_INT_B_T3 
DLY_INT_B_T2 
DLY_INT_B_T1 
DLY_INT_B_T0 
EVENT_COUNT_B 
MAX_DELAY_TIME_B 

Definition at line 439 of file amd8111e.h.

00439              {
00440 
00441         DLY_INT_B_R3            = (1 << 31),
00442         DLY_INT_B_R2            = (1 << 30),
00443         DLY_INT_B_R1            = (1 << 29),
00444         DLY_INT_B_R0            = (1 << 28),
00445         DLY_INT_B_T3            = (1 << 27),
00446         DLY_INT_B_T2            = (1 << 26),
00447         DLY_INT_B_T1            = (1 << 25),
00448         DLY_INT_B_T0            = ( 1 << 24),
00449         EVENT_COUNT_B           = (0xF << 16) | (0x1 << 20),/* 20:16 */
00450         MAX_DELAY_TIME_B        = (0xF << 0) | (0xF << 4) | (1 << 8)| 
00451                                   (1 << 9) | (1 << 10), /* 10:0 */
00452 }DLY_INT_B_BITS;

enum FLOW_CONTROL_BITS

Enumerator:
PAUSE_LEN_CHG 
FTPE 
FRPE 
NAPA 
NPA 
FIXP 
FCCMD 
PAUSE_LEN 

Definition at line 456 of file amd8111e.h.

00456              {
00457 
00458         PAUSE_LEN_CHG           = (1 << 30),
00459         FTPE                    = (1 << 22),
00460         FRPE                    = (1 << 21),
00461         NAPA                    = (1 << 20),
00462         NPA                     = (1 << 19),
00463         FIXP                    = ( 1 << 18),
00464         FCCMD                   = ( 1 << 16),
00465         PAUSE_LEN               = (0xF << 0) | (0xF << 4) |( 0xF << 8) |                                          (0xF << 12),  /* 15:0 */
00466 
00467 }FLOW_CONTROL_BITS;

enum PHY_ACCESS_BITS

Enumerator:
PHY_CMD_ACTIVE 
PHY_WR_CMD 
PHY_RD_CMD 
PHY_RD_ERR 
PHY_PRE_SUP 
PHY_ADDR 
PHY_REG_ADDR 
PHY_DATA 

Definition at line 470 of file amd8111e.h.

00470              {
00471 
00472         PHY_CMD_ACTIVE          = (1 << 31),
00473         PHY_WR_CMD              = (1 << 30),
00474         PHY_RD_CMD              = (1 << 29),
00475         PHY_RD_ERR              = (1 << 28),
00476         PHY_PRE_SUP             = (1 << 27),
00477         PHY_ADDR                = (1 << 21) | (1 << 22) | (1 << 23)|
00478                                         (1 << 24) |(1 << 25),/* 25:21 */
00479         PHY_REG_ADDR            = (1 << 16) | (1 << 17) | (1 << 18)|                                                    (1 << 19) | (1 << 20),/* 20:16 */
00480         PHY_DATA                = (0xF << 0)|(0xF << 4) |(0xF << 8)|
00481                                         (0xF << 12),/* 15:0 */
00482 
00483 }PHY_ACCESS_BITS;

enum PMAT0_BITS

Enumerator:
PMR_ACTIVE 
PMR_WR_CMD 
PMR_RD_CMD 
PMR_BANK 
PMR_ADDR 
PMR_B4 

Definition at line 487 of file amd8111e.h.

00487              {
00488         PMR_ACTIVE              = (1 << 31),
00489         PMR_WR_CMD              = (1 << 30),
00490         PMR_RD_CMD              = (1 << 29),
00491         PMR_BANK                = (1 <<28),
00492         PMR_ADDR                = (0xF << 16)|(1 << 20)|(1 << 21)|
00493                                         (1 << 22),/* 22:16 */
00494         PMR_B4                  = (0xF << 0) | (0xF << 4),/* 15:0 */
00495 }PMAT0_BITS;

enum PMAT1_BITS

Enumerator:
PMR_B3 
PMR_B2 
PMR_B1 
PMR_B0 

Definition at line 499 of file amd8111e.h.

00499              {
00500         PMR_B3                  = (0xF << 24) | (0xF <<28),/* 31:24 */
00501         PMR_B2                  = (0xF << 16) |(0xF << 20),/* 23:16 */
00502         PMR_B1                  = (0xF << 8) | (0xF <<12), /* 15:8 */
00503         PMR_B0                  = (0xF << 0)|(0xF << 4),/* 7:0 */
00504 }PMAT1_BITS;

enum TX_FLAG_BITS

Enumerator:
OWN_BIT 
ADD_FCS_BIT 
LTINT_BIT 
STP_BIT 
ENP_BIT 
KILL_BIT 
TCC_VLAN_INSERT 
TCC_VLAN_REPLACE 

Definition at line 577 of file amd8111e.h.

00577              {
00578 
00579         OWN_BIT         =       (1 << 15),
00580         ADD_FCS_BIT     =       (1 << 13),
00581         LTINT_BIT       =       (1 << 12),
00582         STP_BIT         =       (1 << 9),
00583         ENP_BIT         =       (1 << 8),
00584         KILL_BIT        =       (1 << 6),
00585         TCC_VLAN_INSERT =       (1 << 1),
00586         TCC_VLAN_REPLACE =      (1 << 1) |( 1<< 0),
00587 
00588 }TX_FLAG_BITS;

enum RX_FLAG_BITS

Enumerator:
ERR_BIT 
FRAM_BIT 
OFLO_BIT 
CRC_BIT 
PAM_BIT 
LAFM_BIT 
BAM_BIT 
TT_VLAN_TAGGED 
TT_PRTY_TAGGED 

Definition at line 590 of file amd8111e.h.

00590              {
00591         ERR_BIT         =       (1 << 14),
00592         FRAM_BIT        =       (1 << 13),
00593         OFLO_BIT        =       (1 << 12),
00594         CRC_BIT         =       (1 << 11),
00595         PAM_BIT         =       (1 << 6),
00596         LAFM_BIT        =       (1 << 5),
00597         BAM_BIT         =       (1 << 4),
00598         TT_VLAN_TAGGED  =       (1 << 3) |(1 << 2),/* 0x000 */
00599         TT_PRTY_TAGGED  =       (1 << 3),/* 0x0008 */
00600 
00601 }RX_FLAG_BITS;

enum EXT_PHY_OPTION

Enumerator:
SPEED_AUTONEG 
SPEED10_HALF 
SPEED10_FULL 
SPEED100_HALF 
SPEED100_FULL 

Definition at line 621 of file amd8111e.h.

00621              {
00622         SPEED_AUTONEG,
00623         SPEED10_HALF,
00624         SPEED10_FULL,
00625         SPEED100_HALF,
00626         SPEED100_FULL,
00627 }EXT_PHY_OPTION;

Function Documentation

FILE_LICENCE ( GPL2_OR_LATER   ) 

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