UefiPxe.h
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00021 #ifndef __EFI_PXE_H__
00022 #define __EFI_PXE_H__
00023
00024 #pragma pack(1)
00025
00026 #define PXE_BUSTYPE(a, b, c, d) \
00027 ( \
00028 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
00029 ((PXE_UINT32) (a) & 0xFF) \
00030 )
00031
00032
00033
00034
00035 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
00036
00037
00038
00039
00040 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
00041 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
00042 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
00043 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
00044
00045 #define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
00046
00047 #define PXE_SWAP_UINT32(n) \
00048 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
00049 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \
00050 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \
00051 (((PXE_UINT32)(n) & 0xFF000000) >> 24))
00052
00053 #define PXE_SWAP_UINT64(n) \
00054 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
00055 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
00056 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
00057 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \
00058 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \
00059 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
00060 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
00061 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
00062
00063
00064 #define PXE_CPBSIZE_NOT_USED 0
00065 #define PXE_DBSIZE_NOT_USED 0
00066 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0
00067 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0
00068 #define PXE_CONST CONST
00069
00070 #define PXE_VOLATILE volatile
00071
00072 typedef VOID PXE_VOID;
00073 typedef UINT8 PXE_UINT8;
00074 typedef UINT16 PXE_UINT16;
00075 typedef UINT32 PXE_UINT32;
00076 typedef UINTN PXE_UINTN;
00077
00078
00079
00080
00081 typedef UINT64 PXE_UINT64;
00082
00083 typedef PXE_UINT8 PXE_BOOL;
00084 #define PXE_FALSE 0
00085 #define PXE_TRUE (!PXE_FALSE)
00086
00087 typedef PXE_UINT16 PXE_OPCODE;
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00089
00090
00091
00092 #define PXE_OPCODE_GET_STATE 0x0000
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00096
00097 #define PXE_OPCODE_START 0x0001
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00102 #define PXE_OPCODE_STOP 0x0002
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00107 #define PXE_OPCODE_GET_INIT_INFO 0x0003
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00112 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004
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00117 #define PXE_OPCODE_INITIALIZE 0x0005
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00122 #define PXE_OPCODE_RESET 0x0006
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00126
00127 #define PXE_OPCODE_SHUTDOWN 0x0007
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00131
00132 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
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00137 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009
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00142 #define PXE_OPCODE_STATION_ADDRESS 0x000A
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00146
00147 #define PXE_OPCODE_STATISTICS 0x000B
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00151
00152 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
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00157 #define PXE_OPCODE_NVDATA 0x000D
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00162 #define PXE_OPCODE_GET_STATUS 0x000E
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00166
00167 #define PXE_OPCODE_FILL_HEADER 0x000F
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00172 #define PXE_OPCODE_TRANSMIT 0x0010
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00177 #define PXE_OPCODE_RECEIVE 0x0011
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00181
00182 #define PXE_OPCODE_LAST_VALID 0x0011
00183
00184 typedef PXE_UINT16 PXE_OPFLAGS;
00185
00186 #define PXE_OPFLAGS_NOT_USED 0x0000
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00217 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
00218 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
00219 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
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00221
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00225 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
00226 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
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00240 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
00241 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
00242 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
00243 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000
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00249 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
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00255 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
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00261 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
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00267 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
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00276 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
00277 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
00278 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
00279 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
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00285 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
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00290
00291 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
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00296
00297 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
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00304 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
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00309 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
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00315 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
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00320 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
00321 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
00322 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
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00327 #define PXE_OPFLAGS_STATISTICS_READ 0x0000
00328 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001
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00336 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
00337 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
00338 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
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00345
00346 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
00347 #define PXE_OPFLAGS_NVDATA_READ 0x0000
00348 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001
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00359 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
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00369 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
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00374 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
00375 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
00376 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
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00386 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
00387 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
00388 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
00389
00390 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
00391 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
00392 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
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00403 typedef PXE_UINT16 PXE_STATFLAGS;
00404
00405 #define PXE_STATFLAGS_INITIALIZE 0x0000
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00415 #define PXE_STATFLAGS_STATUS_MASK 0xC000
00416 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
00417 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000
00418 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
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00423 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003
00424 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
00425 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
00426 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
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00437 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
00438 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
00439 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
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00444 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
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00449 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
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00462 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
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00467 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
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00472 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
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00481 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
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00486 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
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00492 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
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00497 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
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00502 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
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00534 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
00535 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
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00540 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
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00545 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
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00550 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
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00555 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
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00561 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
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00567 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
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00587 typedef PXE_UINT16 PXE_STATCODE;
00588
00589 #define PXE_STATCODE_INITIALIZE 0x0000
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00595 #define PXE_STATCODE_SUCCESS 0x0000
00596
00597 #define PXE_STATCODE_INVALID_CDB 0x0001
00598 #define PXE_STATCODE_INVALID_CPB 0x0002
00599 #define PXE_STATCODE_BUSY 0x0003
00600 #define PXE_STATCODE_QUEUE_FULL 0x0004
00601 #define PXE_STATCODE_ALREADY_STARTED 0x0005
00602 #define PXE_STATCODE_NOT_STARTED 0x0006
00603 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007
00604 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
00605 #define PXE_STATCODE_NOT_INITIALIZED 0x0009
00606 #define PXE_STATCODE_DEVICE_FAILURE 0x000A
00607 #define PXE_STATCODE_NVDATA_FAILURE 0x000B
00608 #define PXE_STATCODE_UNSUPPORTED 0x000C
00609 #define PXE_STATCODE_BUFFER_FULL 0x000D
00610 #define PXE_STATCODE_INVALID_PARAMETER 0x000E
00611 #define PXE_STATCODE_INVALID_UNDI 0x000F
00612 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
00613 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
00614 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
00615 #define PXE_STATCODE_NO_DATA 0x0013
00616
00617 typedef PXE_UINT16 PXE_IFNUM;
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00622 #define PXE_IFNUM_START 0x0000
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00628 #define PXE_IFNUM_INVALID 0x0000
00629
00630 typedef PXE_UINT16 PXE_CONTROL;
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00639 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
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00648 #define PXE_CONTROL_LINK 0x0001
00649 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
00650
00651 typedef PXE_UINT8 PXE_FRAME_TYPE;
00652
00653 #define PXE_FRAME_TYPE_NONE 0x00
00654 #define PXE_FRAME_TYPE_UNICAST 0x01
00655 #define PXE_FRAME_TYPE_BROADCAST 0x02
00656 #define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
00657 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04
00658 #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
00659
00660 #define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST
00661
00662 typedef PXE_UINT32 PXE_IPV4;
00663
00664 typedef PXE_UINT32 PXE_IPV6[4];
00665 #define PXE_MAC_LENGTH 32
00666
00667 typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
00668
00669 typedef PXE_UINT8 PXE_IFTYPE;
00670 typedef UINT16 PXE_MEDIA_PROTOCOL;
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00699 #define PXE_IFTYPE_ETHERNET 0x01
00700 #define PXE_IFTYPE_TOKENRING 0x04
00701 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12
00702
00703 typedef struct s_pxe_hw_undi {
00704 PXE_UINT32 Signature;
00705 PXE_UINT8 Len;
00706 PXE_UINT8 Fudge;
00707 PXE_UINT8 Rev;
00708 PXE_UINT8 IFcnt;
00709 PXE_UINT8 MajorVer;
00710 PXE_UINT8 MinorVer;
00711 PXE_UINT16 reserved;
00712 PXE_UINT32 Implementation;
00713
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00718 } PXE_HW_UNDI;
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00727 #define PXE_HWSTAT_STATE_MASK 0xC0000000
00728 #define PXE_HWSTAT_BUSY 0xC0000000
00729 #define PXE_HWSTAT_INITIALIZED 0x80000000
00730 #define PXE_HWSTAT_STARTED 0x40000000
00731 #define PXE_HWSTAT_STOPPED 0x00000000
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00736 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
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00741 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
00742 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
00743 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
00744 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
00745 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
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00750 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
00751 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
00752 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
00753 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
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00758 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
00759 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
00760 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
00761 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
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00771 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000
00772 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000
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00777 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
00778 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
00779 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
00780 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
00781 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
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00783
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00785
00786 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
00787 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
00788 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
00789 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
00790
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00793
00794 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
00795 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
00796 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
00797 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
00798
00799 typedef struct s_pxe_sw_undi {
00800 PXE_UINT32 Signature;
00801 PXE_UINT8 Len;
00802 PXE_UINT8 Fudge;
00803 PXE_UINT8 Rev;
00804 PXE_UINT8 IFcnt;
00805 PXE_UINT8 MajorVer;
00806 PXE_UINT8 MinorVer;
00807 PXE_UINT16 reserved1;
00808 PXE_UINT32 Implementation;
00809 PXE_UINT64 EntryPoint;
00810 PXE_UINT8 reserved2[3];
00811 PXE_UINT8 BusCnt;
00812 PXE_UINT32 BusType[1];
00813 } PXE_SW_UNDI;
00814
00815 typedef union u_pxe_undi {
00816 PXE_HW_UNDI hw;
00817 PXE_SW_UNDI sw;
00818 } PXE_UNDI;
00819
00820
00821
00822
00823 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
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00825
00826
00827
00828 #define PXE_ROMID_REV 0x02
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00834
00835 #define PXE_ROMID_MAJORVER 0x03
00836 #define PXE_ROMID_MINORVER 0x01
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00840
00841 #define PXE_ROMID_IMP_HW_UNDI 0x80000000
00842 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
00843 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
00844 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
00845 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
00846 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
00847 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
00848 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
00849 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
00850 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
00851 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
00852 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
00853 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
00854 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
00855 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
00856 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
00857 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
00858 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
00859 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
00860 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
00861 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
00862 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
00863
00864 typedef struct s_pxe_cdb {
00865 PXE_OPCODE OpCode;
00866 PXE_OPFLAGS OpFlags;
00867 PXE_UINT16 CPBsize;
00868 PXE_UINT16 DBsize;
00869 PXE_UINT64 CPBaddr;
00870 PXE_UINT64 DBaddr;
00871 PXE_STATCODE StatCode;
00872 PXE_STATFLAGS StatFlags;
00873 PXE_UINT16 IFnum;
00874 PXE_CONTROL Control;
00875 } PXE_CDB;
00876
00877 typedef union u_pxe_ip_addr {
00878 PXE_IPV6 IPv6;
00879 PXE_IPV4 IPv4;
00880 } PXE_IP_ADDR;
00881
00882 typedef union pxe_device {
00883
00884
00885
00886
00887
00888
00889 struct {
00890
00891
00892
00893
00894 PXE_UINT32 BusType;
00895
00896
00897
00898
00899 PXE_UINT16 Bus;
00900 PXE_UINT8 Device;
00901 PXE_UINT8 Function;
00902 }
00903 PCI, PCC;
00904
00905 } PXE_DEVICE;
00906
00907
00908
00909
00910 #define MAX_PCI_CONFIG_LEN 64
00911 #define MAX_EEPROM_LEN 128
00912 #define MAX_XMIT_BUFFERS 32
00913 #define MAX_MCAST_ADDRESS_CNT 8
00914
00915 typedef struct s_pxe_cpb_start_30 {
00916
00917
00918
00919
00920
00921
00922
00923
00924
00925
00926 UINT64 Delay;
00927
00928
00929
00930
00931
00932
00933
00934
00935
00936
00937
00938
00939
00940
00941
00942 UINT64 Block;
00943
00944
00945
00946
00947
00948
00949
00950
00951
00952
00953
00954
00955
00956 UINT64 Virt2Phys;
00957
00958
00959
00960
00961
00962
00963
00964
00965
00966
00967 UINT64 Mem_IO;
00968 } PXE_CPB_START_30;
00969
00970 typedef struct s_pxe_cpb_start_31 {
00971
00972
00973
00974
00975
00976
00977
00978
00979
00980
00981 UINT64 Delay;
00982
00983
00984
00985
00986
00987
00988
00989
00990
00991
00992
00993
00994
00995
00996
00997 UINT64 Block;
00998
00999
01000
01001
01002
01003
01004
01005
01006
01007
01008
01009
01010
01011 UINT64 Virt2Phys;
01012
01013
01014
01015
01016
01017
01018
01019
01020
01021
01022 UINT64 Mem_IO;
01023
01024
01025
01026
01027
01028
01029
01030
01031
01032
01033
01034
01035
01036
01037
01038
01039 UINT64 Map_Mem;
01040
01041
01042
01043
01044
01045
01046
01047
01048
01049
01050 UINT64 UnMap_Mem;
01051
01052
01053
01054
01055
01056
01057
01058
01059
01060
01061
01062 UINT64 Sync_Mem;
01063
01064
01065
01066
01067
01068
01069
01070 UINT64 Unique_ID;
01071 } PXE_CPB_START_31;
01072
01073 #define TO_AND_FROM_DEVICE 0
01074 #define FROM_DEVICE 1
01075 #define TO_DEVICE 2
01076
01077 #define PXE_DELAY_MILLISECOND 1000
01078 #define PXE_DELAY_SECOND 1000000
01079 #define PXE_IO_READ 0
01080 #define PXE_IO_WRITE 1
01081 #define PXE_MEM_READ 2
01082 #define PXE_MEM_WRITE 4
01083
01084 typedef struct s_pxe_db_get_init_info {
01085
01086
01087
01088
01089
01090
01091
01092
01093 PXE_UINT32 MemoryRequired;
01094
01095
01096
01097
01098 PXE_UINT32 FrameDataLen;
01099
01100
01101
01102
01103
01104
01105 PXE_UINT32 LinkSpeeds[4];
01106
01107
01108
01109
01110 PXE_UINT32 NvCount;
01111
01112
01113
01114
01115 PXE_UINT16 NvWidth;
01116
01117
01118
01119
01120
01121
01122 PXE_UINT16 MediaHeaderLen;
01123
01124
01125
01126
01127 PXE_UINT16 HWaddrLen;
01128
01129
01130
01131
01132
01133 PXE_UINT16 MCastFilterCnt;
01134
01135
01136
01137
01138
01139
01140
01141
01142 PXE_UINT16 TxBufCnt;
01143 PXE_UINT16 TxBufSize;
01144 PXE_UINT16 RxBufCnt;
01145 PXE_UINT16 RxBufSize;
01146
01147
01148
01149
01150
01151
01152 PXE_UINT8 IFtype;
01153
01154
01155
01156
01157 PXE_UINT8 SupportedDuplexModes;
01158
01159
01160
01161
01162 PXE_UINT8 SupportedLoopBackModes;
01163 } PXE_DB_GET_INIT_INFO;
01164
01165 #define PXE_MAX_TXRX_UNIT_ETHER 1500
01166
01167 #define PXE_HWADDR_LEN_ETHER 0x0006
01168 #define PXE_MAC_HEADER_LEN_ETHER 0x000E
01169
01170 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
01171 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
01172
01173 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
01174 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
01175
01176 typedef struct s_pxe_pci_config_info {
01177
01178
01179
01180
01181 UINT32 BusType;
01182
01183
01184
01185
01186
01187 UINT16 Bus;
01188 UINT8 Device;
01189 UINT8 Function;
01190
01191
01192
01193
01194
01195 union {
01196 UINT8 Byte[256];
01197 UINT16 Word[128];
01198 UINT32 Dword[64];
01199 } Config;
01200 } PXE_PCI_CONFIG_INFO;
01201
01202 typedef struct s_pxe_pcc_config_info {
01203
01204
01205
01206
01207 PXE_UINT32 BusType;
01208
01209
01210
01211
01212
01213 PXE_UINT16 Bus;
01214 PXE_UINT8 Device;
01215 PXE_UINT8 Function;
01216
01217
01218
01219
01220
01221 union {
01222 PXE_UINT8 Byte[256];
01223 PXE_UINT16 Word[128];
01224 PXE_UINT32 Dword[64];
01225 } Config;
01226 } PXE_PCC_CONFIG_INFO;
01227
01228 typedef union u_pxe_db_get_config_info {
01229 PXE_PCI_CONFIG_INFO pci;
01230 PXE_PCC_CONFIG_INFO pcc;
01231 } PXE_DB_GET_CONFIG_INFO;
01232
01233 typedef struct s_pxe_cpb_initialize {
01234
01235
01236
01237
01238
01239 PXE_UINT64 MemoryAddr;
01240
01241
01242
01243
01244
01245 PXE_UINT32 MemoryLength;
01246
01247
01248
01249
01250
01251
01252 PXE_UINT32 LinkSpeed;
01253
01254
01255
01256
01257
01258
01259
01260
01261
01262
01263
01264 PXE_UINT16 TxBufCnt;
01265 PXE_UINT16 TxBufSize;
01266 PXE_UINT16 RxBufCnt;
01267 PXE_UINT16 RxBufSize;
01268
01269
01270
01271
01272
01273 PXE_UINT8 DuplexMode;
01274
01275 PXE_UINT8 LoopBackMode;
01276 } PXE_CPB_INITIALIZE;
01277
01278 #define PXE_DUPLEX_DEFAULT 0x00
01279 #define PXE_FORCE_FULL_DUPLEX 0x01
01280 #define PXE_ENABLE_FULL_DUPLEX 0x02
01281 #define PXE_FORCE_HALF_DUPLEX 0x04
01282 #define PXE_DISABLE_FULL_DUPLEX 0x08
01283
01284 #define LOOPBACK_NORMAL 0
01285 #define LOOPBACK_INTERNAL 1
01286 #define LOOPBACK_EXTERNAL 2
01287
01288 typedef struct s_pxe_db_initialize {
01289
01290
01291
01292
01293
01294
01295
01296
01297 PXE_UINT32 MemoryUsed;
01298
01299
01300
01301
01302
01303 PXE_UINT16 TxBufCnt;
01304 PXE_UINT16 TxBufSize;
01305 PXE_UINT16 RxBufCnt;
01306 PXE_UINT16 RxBufSize;
01307 } PXE_DB_INITIALIZE;
01308
01309 typedef struct s_pxe_cpb_receive_filters {
01310
01311
01312
01313
01314 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
01315 } PXE_CPB_RECEIVE_FILTERS;
01316
01317 typedef struct s_pxe_db_receive_filters {
01318
01319
01320
01321 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
01322 } PXE_DB_RECEIVE_FILTERS;
01323
01324 typedef struct s_pxe_cpb_station_address {
01325
01326
01327
01328
01329 PXE_MAC_ADDR StationAddr;
01330 } PXE_CPB_STATION_ADDRESS;
01331
01332 typedef struct s_pxe_dpb_station_address {
01333
01334
01335
01336 PXE_MAC_ADDR StationAddr;
01337
01338
01339
01340
01341 PXE_MAC_ADDR BroadcastAddr;
01342
01343
01344
01345
01346 PXE_MAC_ADDR PermanentAddr;
01347 } PXE_DB_STATION_ADDRESS;
01348
01349 typedef struct s_pxe_db_statistics {
01350
01351
01352
01353
01354
01355
01356
01357
01358
01359 PXE_UINT64 Supported;
01360
01361
01362
01363
01364 PXE_UINT64 Data[64];
01365 } PXE_DB_STATISTICS;
01366
01367
01368
01369
01370
01371 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
01372
01373
01374
01375
01376 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
01377
01378
01379
01380
01381
01382 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
01383
01384
01385
01386
01387
01388 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
01389
01390
01391
01392
01393 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
01394
01395
01396
01397
01398 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
01399
01400
01401
01402
01403 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
01404
01405
01406
01407
01408 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
01409
01410
01411
01412
01413 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
01414
01415
01416
01417
01418
01419 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
01420
01421
01422
01423
01424 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
01425 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
01426 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
01427 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
01428 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
01429 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
01430 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
01431 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
01432 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
01433 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
01434
01435
01436
01437
01438 #define PXE_STATISTICS_COLLISIONS 0x14
01439
01440
01441
01442
01443 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
01444
01445 typedef struct s_pxe_cpb_mcast_ip_to_mac {
01446
01447
01448
01449 PXE_IP_ADDR IP;
01450 } PXE_CPB_MCAST_IP_TO_MAC;
01451
01452 typedef struct s_pxe_db_mcast_ip_to_mac {
01453
01454
01455
01456 PXE_MAC_ADDR MAC;
01457 } PXE_DB_MCAST_IP_TO_MAC;
01458
01459 typedef struct s_pxe_cpb_nvdata_sparse {
01460
01461
01462
01463 struct {
01464
01465
01466
01467 PXE_UINT32 Addr;
01468
01469
01470
01471
01472 union {
01473 PXE_UINT8 Byte;
01474 PXE_UINT16 Word;
01475 PXE_UINT32 Dword;
01476 } Data;
01477 } Item[MAX_EEPROM_LEN];
01478 } PXE_CPB_NVDATA_SPARSE;
01479
01480
01481
01482
01483
01484 typedef union u_pxe_cpb_nvdata_bulk {
01485
01486
01487
01488 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
01489
01490
01491
01492
01493 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
01494
01495
01496
01497
01498 PXE_UINT32 Dword[MAX_EEPROM_LEN];
01499 } PXE_CPB_NVDATA_BULK;
01500
01501 typedef struct s_pxe_db_nvdata {
01502
01503
01504
01505 union {
01506
01507
01508
01509 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
01510
01511
01512
01513
01514 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
01515
01516
01517
01518
01519 PXE_UINT32 Dword[MAX_EEPROM_LEN];
01520 } Data;
01521 } PXE_DB_NVDATA;
01522
01523 typedef struct s_pxe_db_get_status {
01524
01525
01526
01527
01528 PXE_UINT32 RxFrameLen;
01529
01530
01531
01532
01533 PXE_UINT32 reserved;
01534
01535
01536
01537
01538 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];
01539 } PXE_DB_GET_STATUS;
01540
01541 typedef struct s_pxe_cpb_fill_header {
01542
01543
01544
01545
01546 PXE_MAC_ADDR SrcAddr;
01547 PXE_MAC_ADDR DestAddr;
01548
01549
01550
01551
01552
01553 PXE_UINT64 MediaHeader;
01554
01555
01556
01557
01558 PXE_UINT32 PacketLen;
01559
01560
01561
01562
01563
01564
01565 PXE_UINT16 Protocol;
01566
01567
01568
01569
01570 PXE_UINT16 MediaHeaderLen;
01571 } PXE_CPB_FILL_HEADER;
01572
01573 #define PXE_PROTOCOL_ETHERNET_IP 0x0800
01574 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
01575 #define MAX_XMIT_FRAGMENTS 16
01576
01577 typedef struct s_pxe_cpb_fill_header_fragmented {
01578
01579
01580
01581
01582 PXE_MAC_ADDR SrcAddr;
01583 PXE_MAC_ADDR DestAddr;
01584
01585
01586
01587
01588 PXE_UINT32 PacketLen;
01589
01590
01591
01592
01593
01594
01595 PXE_MEDIA_PROTOCOL Protocol;
01596
01597
01598
01599
01600 PXE_UINT16 MediaHeaderLen;
01601
01602
01603
01604
01605 PXE_UINT16 FragCnt;
01606
01607
01608
01609
01610 PXE_UINT16 reserved;
01611
01612
01613
01614
01615
01616 struct {
01617
01618
01619
01620 PXE_UINT64 FragAddr;
01621
01622
01623
01624
01625 PXE_UINT32 FragLen;
01626
01627
01628
01629
01630 PXE_UINT32 reserved;
01631 } FragDesc[MAX_XMIT_FRAGMENTS];
01632 }
01633 PXE_CPB_FILL_HEADER_FRAGMENTED;
01634
01635 typedef struct s_pxe_cpb_transmit {
01636
01637
01638
01639
01640 PXE_UINT64 FrameAddr;
01641
01642
01643
01644
01645
01646 PXE_UINT32 DataLen;
01647
01648
01649
01650
01651 PXE_UINT16 MediaheaderLen;
01652
01653
01654
01655
01656 PXE_UINT16 reserved;
01657 } PXE_CPB_TRANSMIT;
01658
01659 typedef struct s_pxe_cpb_transmit_fragments {
01660
01661
01662
01663 PXE_UINT32 FrameLen;
01664
01665
01666
01667
01668 PXE_UINT16 MediaheaderLen;
01669
01670
01671
01672
01673 PXE_UINT16 FragCnt;
01674
01675
01676
01677
01678
01679 struct {
01680
01681
01682
01683 PXE_UINT64 FragAddr;
01684
01685
01686
01687
01688 PXE_UINT32 FragLen;
01689
01690
01691
01692
01693 PXE_UINT32 reserved;
01694 } FragDesc[MAX_XMIT_FRAGMENTS];
01695 }
01696 PXE_CPB_TRANSMIT_FRAGMENTS;
01697
01698 typedef struct s_pxe_cpb_receive {
01699
01700
01701
01702
01703 PXE_UINT64 BufferAddr;
01704
01705
01706
01707
01708
01709
01710 PXE_UINT32 BufferLen;
01711
01712
01713
01714
01715 PXE_UINT32 reserved;
01716 } PXE_CPB_RECEIVE;
01717
01718 typedef struct s_pxe_db_receive {
01719
01720
01721
01722 PXE_MAC_ADDR SrcAddr;
01723 PXE_MAC_ADDR DestAddr;
01724
01725
01726
01727
01728
01729
01730 PXE_UINT32 FrameLen;
01731
01732
01733
01734
01735 PXE_MEDIA_PROTOCOL Protocol;
01736
01737
01738
01739
01740 PXE_UINT16 MediaHeaderLen;
01741
01742
01743
01744
01745 PXE_FRAME_TYPE Type;
01746
01747
01748
01749
01750 PXE_UINT8 reserved[7];
01751
01752 } PXE_DB_RECEIVE;
01753
01754 #pragma pack()
01755
01756 #endif