00001 /* 00002 This software is available to you under a choice of one of two 00003 licenses. You may choose to be licensed under the terms of the GNU 00004 General Public License (GPL) Version 2, available at 00005 <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD 00006 license, available in the LICENSE.TXT file accompanying this 00007 software. These details are also available at 00008 <http://openib.org/license.html>. 00009 00010 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 00011 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00012 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 00013 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 00014 BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 00015 ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 00016 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 00017 SOFTWARE. 00018 00019 Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. 00020 */ 00021 00022 FILE_LICENCE ( GPL2_ONLY ); 00023 00024 /*** 00025 *** This file was generated at "Mon Apr 16 23:22:02 2007" 00026 *** by: 00027 *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix hermonprm_ -bits -fixnames MT25408_PRM.csp 00028 ***/ 00029 00030 #ifndef H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 00031 #define H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 00032 00033 /* UD Address Vector */ 00034 00035 struct hermonprm_ud_address_vector_st { /* Little Endian */ 00036 pseudo_bit_t pd[0x00018]; /* Protection Domain */ 00037 pseudo_bit_t port_number[0x00002]; /* Port number 00038 1 - Port 1 00039 2 - Port 2 00040 other - reserved */ 00041 pseudo_bit_t reserved0[0x00005]; 00042 pseudo_bit_t fl[0x00001]; /* force loopback */ 00043 /* -------------- */ 00044 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 00045 pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 00046 pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 00047 pseudo_bit_t reserved1[0x00008]; 00048 /* -------------- */ 00049 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 00050 pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 00051 0 - 4X injection rate 00052 1 - 1X injection rate 00053 other - reserved 00054 */ 00055 pseudo_bit_t reserved2[0x00004]; 00056 pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table 00057 mgid_index = (port_number-1) * 2^log_max_gid + gid_index 00058 Where: 00059 1. log_max_gid is taken from QUERY_DEV_CAP command 00060 2. gid_index is the index to the GID table */ 00061 pseudo_bit_t reserved3[0x00009]; 00062 /* -------------- */ 00063 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 00064 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 00065 pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 00066 /* -------------- */ 00067 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 00068 /* -------------- */ 00069 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 00070 /* -------------- */ 00071 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 00072 /* -------------- */ 00073 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ 00074 /* -------------- */ 00075 }; 00076 00077 /* Send doorbell */ 00078 00079 struct hermonprm_send_doorbell_st { /* Little Endian */ 00080 pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ 00081 pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ 00082 pseudo_bit_t reserved0[0x00002]; 00083 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ 00084 pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ 00085 /* -------------- */ 00086 pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ 00087 pseudo_bit_t reserved1[0x00002]; 00088 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 00089 /* -------------- */ 00090 }; 00091 00092 /* Send wqe segment data inline */ 00093 00094 struct hermonprm_wqe_segment_data_inline_st { /* Little Endian */ 00095 pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ 00096 pseudo_bit_t reserved0[0x00015]; 00097 pseudo_bit_t always1[0x00001]; 00098 /* -------------- */ 00099 pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ 00100 pseudo_bit_t reserved1[0x00008]; 00101 /* -------------- */ 00102 pseudo_bit_t reserved2[0x00040]; 00103 /* -------------- */ 00104 }; 00105 00106 /* Send wqe segment data ptr */ 00107 00108 struct hermonprm_wqe_segment_data_ptr_st { /* Little Endian */ 00109 pseudo_bit_t byte_count[0x0001f]; 00110 pseudo_bit_t always0[0x00001]; 00111 /* -------------- */ 00112 pseudo_bit_t l_key[0x00020]; 00113 /* -------------- */ 00114 pseudo_bit_t local_address_h[0x00020]; 00115 /* -------------- */ 00116 pseudo_bit_t local_address_l[0x00020]; 00117 /* -------------- */ 00118 }; 00119 00120 /* Send wqe segment rd */ 00121 00122 struct hermonprm_local_invalidate_segment_st { /* Little Endian */ 00123 pseudo_bit_t reserved0[0x00040]; 00124 /* -------------- */ 00125 pseudo_bit_t mem_key[0x00018]; 00126 pseudo_bit_t reserved1[0x00008]; 00127 /* -------------- */ 00128 pseudo_bit_t reserved2[0x000a0]; 00129 /* -------------- */ 00130 }; 00131 00132 /* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */ 00133 00134 struct hermonprm_fast_registration_segment_st { /* Little Endian */ 00135 pseudo_bit_t reserved0[0x0001b]; 00136 pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ 00137 pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ 00138 pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ 00139 pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ 00140 pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ 00141 /* -------------- */ 00142 pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */ 00143 /* -------------- */ 00144 pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */ 00145 /* -------------- */ 00146 pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 00147 page_size should be less than 20. ###michal - field doesn't exsist (see replacement above) */ 00148 pseudo_bit_t reserved1[0x00002]; 00149 pseudo_bit_t zb[0x00001]; /* Zero Based Region ###michal - field doesn't exsist (see replacement above) */ 00150 pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */ 00151 /* -------------- */ 00152 pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ 00153 /* -------------- */ 00154 pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ 00155 /* -------------- */ 00156 pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ 00157 /* -------------- */ 00158 pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ 00159 /* -------------- */ 00160 }; 00161 00162 /* Send wqe segment atomic */ 00163 00164 struct hermonprm_wqe_segment_atomic_st { /* Little Endian */ 00165 pseudo_bit_t swap_add_h[0x00020]; 00166 /* -------------- */ 00167 pseudo_bit_t swap_add_l[0x00020]; 00168 /* -------------- */ 00169 pseudo_bit_t compare_h[0x00020]; 00170 /* -------------- */ 00171 pseudo_bit_t compare_l[0x00020]; 00172 /* -------------- */ 00173 }; 00174 00175 /* Send wqe segment remote address */ 00176 00177 struct hermonprm_wqe_segment_remote_address_st { /* Little Endian */ 00178 pseudo_bit_t remote_virt_addr_h[0x00020]; 00179 /* -------------- */ 00180 pseudo_bit_t remote_virt_addr_l[0x00020]; 00181 /* -------------- */ 00182 pseudo_bit_t rkey[0x00020]; 00183 /* -------------- */ 00184 pseudo_bit_t reserved0[0x00020]; 00185 /* -------------- */ 00186 }; 00187 00188 /* end wqe segment bind */ 00189 00190 struct hermonprm_wqe_segment_bind_st { /* Little Endian */ 00191 pseudo_bit_t reserved0[0x0001d]; 00192 pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ 00193 pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. 00194 */ 00195 pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ 00196 /* -------------- */ 00197 pseudo_bit_t reserved1[0x0001e]; 00198 pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ 00199 pseudo_bit_t type[0x00001]; /* Window type. 00200 0 - Type one window 00201 1 - Type two window 00202 */ 00203 /* -------------- */ 00204 pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ 00205 /* -------------- */ 00206 pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ 00207 /* -------------- */ 00208 pseudo_bit_t start_address_h[0x00020]; 00209 /* -------------- */ 00210 pseudo_bit_t start_address_l[0x00020]; 00211 /* -------------- */ 00212 pseudo_bit_t length_h[0x00020]; 00213 /* -------------- */ 00214 pseudo_bit_t length_l[0x00020]; 00215 /* -------------- */ 00216 }; 00217 00218 /* Send wqe segment ud */ 00219 00220 struct hermonprm_wqe_segment_ud_st { /* Little Endian */ 00221 struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 00222 /* -------------- */ 00223 pseudo_bit_t destination_qp[0x00018]; 00224 pseudo_bit_t reserved0[0x00008]; 00225 /* -------------- */ 00226 pseudo_bit_t q_key[0x00020]; 00227 /* -------------- */ 00228 pseudo_bit_t reserved1[0x00040]; 00229 /* -------------- */ 00230 }; 00231 00232 /* Send wqe segment rd */ 00233 00234 struct hermonprm_wqe_segment_rd_st { /* Little Endian */ 00235 pseudo_bit_t destination_qp[0x00018]; 00236 pseudo_bit_t reserved0[0x00008]; 00237 /* -------------- */ 00238 pseudo_bit_t q_key[0x00020]; 00239 /* -------------- */ 00240 pseudo_bit_t reserved1[0x00040]; 00241 /* -------------- */ 00242 }; 00243 00244 /* Send wqe segment ctrl */ 00245 00246 struct hermonprm_wqe_segment_ctrl_send_st { /* Little Endian */ 00247 pseudo_bit_t opcode[0x00005]; 00248 pseudo_bit_t reserved0[0x0001a]; 00249 pseudo_bit_t owner[0x00001]; 00250 /* -------------- */ 00251 pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */ 00252 pseudo_bit_t f[0x00001]; /* fence */ 00253 pseudo_bit_t reserved1[0x00019]; 00254 /* -------------- */ 00255 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 00256 pseudo_bit_t s[0x00001]; /* Remote Solicited Event */ 00257 pseudo_bit_t c[0x00002]; /* completion required: 0b00 - no 0b11 - yes */ 00258 pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ 00259 pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ 00260 pseudo_bit_t reserved2[0x00001]; 00261 pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ 00262 pseudo_bit_t src_remote_buf[0x00018]; 00263 /* -------------- */ 00264 pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ 00265 /* -------------- */ 00266 }; 00267 00268 /* Address Path # ###michal - match to PRM */ 00269 00270 struct hermonprm_address_path_st { /* Little Endian */ 00271 pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ 00272 pseudo_bit_t reserved0[0x00016]; 00273 pseudo_bit_t sv[0x00001]; /* Service VLAN on QP */ 00274 pseudo_bit_t cv[0x00001]; /* Customer VLAN in QP */ 00275 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 00276 /* -------------- */ 00277 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 00278 pseudo_bit_t my_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 00279 pseudo_bit_t grh_ip[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 00280 pseudo_bit_t reserved1[0x00008]; 00281 /* -------------- */ 00282 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 00283 pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 00284 0 - 100% injection rate 00285 1 - 25% injection rate 00286 2 - 12.5% injection rate 00287 3 - 50% injection rate 00288 7: 2.5 Gb/s. 00289 8: 10 Gb/s. 00290 9: 30 Gb/s. 00291 10: 5 Gb/s. 00292 11: 20 Gb/s. 00293 12: 40 Gb/s. 00294 13: 60 Gb/s. 00295 14: 80 Gb/s. 00296 15: 120 Gb/s. */ 00297 pseudo_bit_t reserved2[0x00004]; 00298 pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table */ 00299 pseudo_bit_t reserved3[0x00004]; 00300 pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. 00301 The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ 00302 /* -------------- */ 00303 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 00304 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 00305 pseudo_bit_t reserved4[0x00004]; 00306 /* -------------- */ 00307 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 00308 /* -------------- */ 00309 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 00310 /* -------------- */ 00311 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 00312 /* -------------- */ 00313 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ 00314 /* -------------- */ 00315 pseudo_bit_t reserved5[0x00008]; 00316 pseudo_bit_t sp[0x00001]; /* if set, spoofing protection is enforced on this QP and Ethertype headers are restricted */ 00317 pseudo_bit_t reserved6[0x00002]; 00318 pseudo_bit_t fvl[0x00001]; /* force VLAN */ 00319 pseudo_bit_t fsip[0x00001]; /* force source IP */ 00320 pseudo_bit_t fsm[0x00001]; /* force source MAC */ 00321 pseudo_bit_t reserved7[0x0000a]; 00322 pseudo_bit_t sched_queue[0x00008]; 00323 /* -------------- */ 00324 pseudo_bit_t dmac_47_32[0x00010]; 00325 pseudo_bit_t vlan_index[0x00007]; 00326 pseudo_bit_t reserved8[0x00001]; 00327 pseudo_bit_t counter_index[0x00008];/* Index to a table of counters that counts egress packets and bytes, 0xFF not valid */ 00328 /* -------------- */ 00329 pseudo_bit_t dmac_31_0[0x00020]; 00330 /* -------------- */ 00331 }; 00332 00333 /* HCA Command Register (HCR) #### michal - match PRM */ 00334 00335 struct hermonprm_hca_command_register_st { /* Little Endian */ 00336 pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ 00337 /* -------------- */ 00338 pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ 00339 /* -------------- */ 00340 pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ 00341 /* -------------- */ 00342 pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ 00343 /* -------------- */ 00344 pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ 00345 /* -------------- */ 00346 pseudo_bit_t reserved0[0x00010]; 00347 pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ 00348 /* -------------- */ 00349 pseudo_bit_t opcode[0x0000c]; /* Command opcode */ 00350 pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ 00351 pseudo_bit_t reserved1[0x00005]; 00352 pseudo_bit_t t[0x00001]; /* Toggle */ 00353 pseudo_bit_t e[0x00001]; /* Event Request 00354 0 - Don't report event (software will poll the GO bit) 00355 1 - Report event to EQ when the command completes */ 00356 pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) 00357 Software can write to the HCR only if Go bit is cleared. 00358 Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ 00359 pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) 00360 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ 00361 /* -------------- */ 00362 }; 00363 00364 /* CQ Doorbell */ 00365 00366 struct hermonprm_cq_cmd_doorbell_st { /* Little Endian */ 00367 pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ 00368 pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ 00369 0x0 - Reserved 00370 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. 00371 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. 00372 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated 00373 Other - Reserved */ 00374 pseudo_bit_t reserved0[0x00001]; 00375 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. 00376 This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited 00377 completion or Request notification for multiple completions doorbells after receiving completion notification. 00378 This field is initialized to Zero */ 00379 pseudo_bit_t reserved1[0x00002]; 00380 /* -------------- */ 00381 pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ 00382 /* -------------- */ 00383 }; 00384 00385 /* RD-send doorbell */ 00386 00387 struct hermonprm_rd_send_doorbell_st { /* Little Endian */ 00388 pseudo_bit_t reserved0[0x00008]; 00389 pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) 00390 Must be zero for Nop and Bind operations */ 00391 /* -------------- */ 00392 pseudo_bit_t reserved1[0x00008]; 00393 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 00394 /* -------------- */ 00395 struct hermonprm_send_doorbell_st send_doorbell;/* Send Parameters */ 00396 /* -------------- */ 00397 }; 00398 00399 /* Multicast Group Member QP #### michal - match PRM */ 00400 00401 struct hermonprm_mgmqp_st { /* Little Endian */ 00402 pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ 00403 pseudo_bit_t reserved0[0x00006]; 00404 pseudo_bit_t blck_lb[0x00001]; /* Block self-loopback messages arriving to this qp */ 00405 pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ 00406 /* -------------- */ 00407 }; 00408 00409 /* vsd */ 00410 00411 struct hermonprm_vsd_st { /* Little Endian */ 00412 pseudo_bit_t vsd_dw0[0x00020]; 00413 /* -------------- */ 00414 pseudo_bit_t vsd_dw1[0x00020]; 00415 /* -------------- */ 00416 pseudo_bit_t vsd_dw2[0x00020]; 00417 /* -------------- */ 00418 pseudo_bit_t vsd_dw3[0x00020]; 00419 /* -------------- */ 00420 pseudo_bit_t vsd_dw4[0x00020]; 00421 /* -------------- */ 00422 pseudo_bit_t vsd_dw5[0x00020]; 00423 /* -------------- */ 00424 pseudo_bit_t vsd_dw6[0x00020]; 00425 /* -------------- */ 00426 pseudo_bit_t vsd_dw7[0x00020]; 00427 /* -------------- */ 00428 pseudo_bit_t vsd_dw8[0x00020]; 00429 /* -------------- */ 00430 pseudo_bit_t vsd_dw9[0x00020]; 00431 /* -------------- */ 00432 pseudo_bit_t vsd_dw10[0x00020]; 00433 /* -------------- */ 00434 pseudo_bit_t vsd_dw11[0x00020]; 00435 /* -------------- */ 00436 pseudo_bit_t vsd_dw12[0x00020]; 00437 /* -------------- */ 00438 pseudo_bit_t vsd_dw13[0x00020]; 00439 /* -------------- */ 00440 pseudo_bit_t vsd_dw14[0x00020]; 00441 /* -------------- */ 00442 pseudo_bit_t vsd_dw15[0x00020]; 00443 /* -------------- */ 00444 pseudo_bit_t vsd_dw16[0x00020]; 00445 /* -------------- */ 00446 pseudo_bit_t vsd_dw17[0x00020]; 00447 /* -------------- */ 00448 pseudo_bit_t vsd_dw18[0x00020]; 00449 /* -------------- */ 00450 pseudo_bit_t vsd_dw19[0x00020]; 00451 /* -------------- */ 00452 pseudo_bit_t vsd_dw20[0x00020]; 00453 /* -------------- */ 00454 pseudo_bit_t vsd_dw21[0x00020]; 00455 /* -------------- */ 00456 pseudo_bit_t vsd_dw22[0x00020]; 00457 /* -------------- */ 00458 pseudo_bit_t vsd_dw23[0x00020]; 00459 /* -------------- */ 00460 pseudo_bit_t vsd_dw24[0x00020]; 00461 /* -------------- */ 00462 pseudo_bit_t vsd_dw25[0x00020]; 00463 /* -------------- */ 00464 pseudo_bit_t vsd_dw26[0x00020]; 00465 /* -------------- */ 00466 pseudo_bit_t vsd_dw27[0x00020]; 00467 /* -------------- */ 00468 pseudo_bit_t vsd_dw28[0x00020]; 00469 /* -------------- */ 00470 pseudo_bit_t vsd_dw29[0x00020]; 00471 /* -------------- */ 00472 pseudo_bit_t vsd_dw30[0x00020]; 00473 /* -------------- */ 00474 pseudo_bit_t vsd_dw31[0x00020]; 00475 /* -------------- */ 00476 pseudo_bit_t vsd_dw32[0x00020]; 00477 /* -------------- */ 00478 pseudo_bit_t vsd_dw33[0x00020]; 00479 /* -------------- */ 00480 pseudo_bit_t vsd_dw34[0x00020]; 00481 /* -------------- */ 00482 pseudo_bit_t vsd_dw35[0x00020]; 00483 /* -------------- */ 00484 pseudo_bit_t vsd_dw36[0x00020]; 00485 /* -------------- */ 00486 pseudo_bit_t vsd_dw37[0x00020]; 00487 /* -------------- */ 00488 pseudo_bit_t vsd_dw38[0x00020]; 00489 /* -------------- */ 00490 pseudo_bit_t vsd_dw39[0x00020]; 00491 /* -------------- */ 00492 pseudo_bit_t vsd_dw40[0x00020]; 00493 /* -------------- */ 00494 pseudo_bit_t vsd_dw41[0x00020]; 00495 /* -------------- */ 00496 pseudo_bit_t vsd_dw42[0x00020]; 00497 /* -------------- */ 00498 pseudo_bit_t vsd_dw43[0x00020]; 00499 /* -------------- */ 00500 pseudo_bit_t vsd_dw44[0x00020]; 00501 /* -------------- */ 00502 pseudo_bit_t vsd_dw45[0x00020]; 00503 /* -------------- */ 00504 pseudo_bit_t vsd_dw46[0x00020]; 00505 /* -------------- */ 00506 pseudo_bit_t vsd_dw47[0x00020]; 00507 /* -------------- */ 00508 pseudo_bit_t vsd_dw48[0x00020]; 00509 /* -------------- */ 00510 pseudo_bit_t vsd_dw49[0x00020]; 00511 /* -------------- */ 00512 pseudo_bit_t vsd_dw50[0x00020]; 00513 /* -------------- */ 00514 pseudo_bit_t vsd_dw51[0x00020]; 00515 /* -------------- */ 00516 pseudo_bit_t vsd_dw52[0x00020]; 00517 /* -------------- */ 00518 pseudo_bit_t vsd_dw53[0x00020]; 00519 /* -------------- */ 00520 pseudo_bit_t vsd_dw54[0x00020]; 00521 /* -------------- */ 00522 pseudo_bit_t vsd_dw55[0x00020]; 00523 /* -------------- */ 00524 }; 00525 00526 /* UAR Parameters */ 00527 00528 struct hermonprm_uar_params_st { /* Little Endian */ 00529 pseudo_bit_t reserved0[0x00040]; 00530 /* -------------- */ 00531 pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. 00532 Size of UAR Page is 4KB*2^UAR_Page_Size */ 00533 pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ 00534 pseudo_bit_t reserved1[0x00014]; 00535 /* -------------- */ 00536 pseudo_bit_t reserved2[0x000a0]; 00537 /* -------------- */ 00538 }; 00539 00540 /* Translation and Protection Tables Parameters */ 00541 00542 struct hermonprm_tptparams_st { /* Little Endian */ 00543 pseudo_bit_t dmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32]. 00544 Entry size is 64 bytes. 00545 Table must be aligned to its size. 00546 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00547 /* -------------- */ 00548 pseudo_bit_t dmpt_base_adr_l[0x00020];/* dMPT - Memory Protection Table base physical address [31:0]. 00549 Entry size is 64 bytes. 00550 Table must be aligned to its size. 00551 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00552 /* -------------- */ 00553 pseudo_bit_t log_dmpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the dMPT table. */ 00554 pseudo_bit_t reserved0[0x00002]; 00555 pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - 00556 The field returned in RNR Naks generated when a page fault is detected. 00557 It has no effect when on-demand-paging is not used. */ 00558 pseudo_bit_t reserved1[0x00013]; 00559 /* -------------- */ 00560 pseudo_bit_t reserved2[0x00020]; 00561 /* -------------- */ 00562 pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. 00563 Table must be aligned to its size. 00564 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00565 /* -------------- */ 00566 pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. 00567 Table must be aligned to its size. 00568 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00569 /* -------------- */ 00570 pseudo_bit_t cmpt_base_adr_h[0x00020];/* cMPT - Memory Protection Table base physical address [63:32]. 00571 Entry size is 64 bytes. 00572 Table must be aligned to its size. */ 00573 /* -------------- */ 00574 pseudo_bit_t cmpt_base_adr_l[0x00020];/* cMPT - Memory Protection Table base physical address [31:0]. 00575 Entry size is 64 bytes. 00576 Table must be aligned to its size. */ 00577 /* -------------- */ 00578 }; 00579 00580 /* Multicast Support Parameters #### michal - match PRM */ 00581 00582 struct hermonprm_multicastparam_st { /* Little Endian */ 00583 pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. 00584 The base address must be aligned to the entry size. 00585 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 00586 /* -------------- */ 00587 pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. 00588 The base address must be aligned to the entry size. 00589 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 00590 /* -------------- */ 00591 pseudo_bit_t reserved0[0x00040]; 00592 /* -------------- */ 00593 pseudo_bit_t log_mc_table_entry_sz[0x00005];/* Log2 of the Size of multicast group member (MGM) entry. 00594 Must be greater than 5 (to allow CTRL and GID sections). 00595 That implies the number of QPs per MC table entry. */ 00596 pseudo_bit_t reserved1[0x0000b]; 00597 pseudo_bit_t reserved2[0x00010]; 00598 /* -------------- */ 00599 pseudo_bit_t log_mc_table_hash_sz[0x00005];/* Number of entries in multicast DGID hash table (must be power of 2) 00600 INIT_HCA - the required number of entries 00601 QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ 00602 pseudo_bit_t reserved3[0x0001b]; 00603 /* -------------- */ 00604 pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ 00605 pseudo_bit_t reserved4[0x00013]; 00606 pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function 00607 0 - Default hash function 00608 other - reserved */ 00609 pseudo_bit_t reserved5[0x00005]; 00610 /* -------------- */ 00611 pseudo_bit_t reserved6[0x00020]; 00612 /* -------------- */ 00613 }; 00614 00615 /* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */ 00616 00617 struct hermonprm_qpcbaseaddr_st { /* Little Endian */ 00618 pseudo_bit_t reserved0[0x00080]; 00619 /* -------------- */ 00620 pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] 00621 Table must be aligned on its size */ 00622 /* -------------- */ 00623 pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ 00624 pseudo_bit_t qpc_base_addr_l[0x0001b];/* QPC Base Address [31:7] 00625 Table must be aligned on its size */ 00626 /* -------------- */ 00627 pseudo_bit_t reserved1[0x00040]; 00628 /* -------------- */ 00629 pseudo_bit_t reserved2[0x00040]; 00630 /* -------------- */ 00631 pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] 00632 Table must be aligned on its size 00633 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 00634 /* -------------- */ 00635 pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ 00636 pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] 00637 Table must be aligned on its size 00638 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 00639 /* -------------- */ 00640 pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] 00641 Table must be aligned on its size */ 00642 /* -------------- */ 00643 pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ 00644 pseudo_bit_t cqc_base_addr_l[0x0001b];/* CQC Base Address [31:6] 00645 Table must be aligned on its size */ 00646 /* -------------- */ 00647 pseudo_bit_t reserved3[0x00040]; 00648 /* -------------- */ 00649 pseudo_bit_t altc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32] 00650 Table has same number of entries as QPC table. 00651 Table must be aligned to entry size. */ 00652 /* -------------- */ 00653 pseudo_bit_t altc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0] 00654 Table has same number of entries as QPC table. 00655 Table must be aligned to entry size. */ 00656 /* -------------- */ 00657 pseudo_bit_t reserved4[0x00040]; 00658 /* -------------- */ 00659 pseudo_bit_t auxc_base_addr_h[0x00020]; 00660 /* -------------- */ 00661 pseudo_bit_t auxc_base_addr_l[0x00020]; 00662 /* -------------- */ 00663 pseudo_bit_t reserved5[0x00040]; 00664 /* -------------- */ 00665 pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] 00666 Address may be set to 0xFFFFFFFF if EQs are not supported. 00667 Table must be aligned to entry size. */ 00668 /* -------------- */ 00669 pseudo_bit_t log_num_of_eq[0x00005];/* Log base 2 of number of supported EQs. 00670 Must be 6 or less in InfiniHost-III-EX. */ 00671 pseudo_bit_t eqc_base_addr_l[0x0001b];/* EQC Base Address [31:6] 00672 Address may be set to 0xFFFFFFFF if EQs are not supported. 00673 Table must be aligned to entry size. */ 00674 /* -------------- */ 00675 pseudo_bit_t reserved6[0x00040]; 00676 /* -------------- */ 00677 pseudo_bit_t rdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */ 00678 /* -------------- */ 00679 pseudo_bit_t log_num_rd[0x00003]; /* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */ 00680 pseudo_bit_t reserved7[0x00002]; 00681 pseudo_bit_t rdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0]. 00682 Table must be aligned to RDB entry size (32 bytes). */ 00683 /* -------------- */ 00684 pseudo_bit_t reserved8[0x00040]; 00685 /* -------------- */ 00686 }; 00687 00688 /* Header_Log_Register */ 00689 00690 struct hermonprm_header_log_register_st { /* Little Endian */ 00691 pseudo_bit_t place_holder[0x00020]; 00692 /* -------------- */ 00693 pseudo_bit_t reserved0[0x00060]; 00694 /* -------------- */ 00695 }; 00696 00697 /* Performance Monitors */ 00698 00699 struct hermonprm_performance_monitors_st { /* Little Endian */ 00700 pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ 00701 pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ 00702 pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ 00703 pseudo_bit_t reserved0[0x00001]; 00704 pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00705 pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00706 pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00707 pseudo_bit_t reserved1[0x00001]; 00708 pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00709 pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00710 pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00711 pseudo_bit_t reserved2[0x00001]; 00712 pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00713 pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00714 pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00715 pseudo_bit_t reserved3[0x00001]; 00716 pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ 00717 pseudo_bit_t reserved4[0x00003]; 00718 pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ 00719 pseudo_bit_t reserved5[0x00003]; 00720 /* -------------- */ 00721 pseudo_bit_t clock_counter[0x00020]; 00722 /* -------------- */ 00723 pseudo_bit_t event_counter1[0x00020]; 00724 /* -------------- */ 00725 pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ 00726 /* -------------- */ 00727 }; 00728 00729 /* MLX WQE segment format */ 00730 00731 struct hermonprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ 00732 pseudo_bit_t opcode[0x00005]; /* must be 0xA = SEND */ 00733 pseudo_bit_t reserved0[0x0001a]; 00734 pseudo_bit_t owner[0x00001]; 00735 /* -------------- */ 00736 pseudo_bit_t ds[0x00006]; /* Descriptor Size */ 00737 pseudo_bit_t reserved1[0x0001a]; 00738 /* -------------- */ 00739 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 00740 pseudo_bit_t reserved2[0x00001]; 00741 pseudo_bit_t c[0x00002]; /* Create CQE (for "requested signalling" QP) */ 00742 pseudo_bit_t icrc[0x00001]; /* last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. 1 - Leave last dword as is. */ 00743 pseudo_bit_t reserved3[0x00003]; 00744 pseudo_bit_t sl[0x00004]; 00745 pseudo_bit_t max_statrate[0x00004]; 00746 pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ 00747 pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ 00748 pseudo_bit_t reserved4[0x0000e]; 00749 /* -------------- */ 00750 pseudo_bit_t reserved5[0x00010]; 00751 pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ 00752 /* -------------- */ 00753 }; 00754 00755 /* Send WQE segment format */ 00756 00757 struct hermonprm_send_wqe_segment_st { /* Little Endian */ 00758 struct hermonprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ 00759 /* -------------- */ 00760 struct hermonprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ 00761 /* -------------- */ 00762 struct hermonprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ 00763 /* -------------- */ 00764 struct hermonprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ 00765 /* -------------- */ 00766 pseudo_bit_t reserved0[0x00180]; 00767 /* -------------- */ 00768 struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ 00769 /* -------------- */ 00770 struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ 00771 /* -------------- */ 00772 struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 00773 /* -------------- */ 00774 struct hermonprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ 00775 /* -------------- */ 00776 struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ 00777 /* -------------- */ 00778 struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ 00779 /* -------------- */ 00780 pseudo_bit_t reserved1[0x00200]; 00781 /* -------------- */ 00782 }; 00783 00784 /* QP and EE Context Entry */ 00785 00786 struct hermonprm_queue_pair_ee_context_entry_st { /* Little Endian */ 00787 pseudo_bit_t reserved0[0x00008]; 00788 pseudo_bit_t reserved1[0x00001]; 00789 pseudo_bit_t reserved2[0x00002]; 00790 pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) 00791 11-Migrated 00792 00-Armed 00793 01-Rearm 00794 10-Reserved 00795 Should be set to 11 for UD QPs and for QPs which do not support APM */ 00796 pseudo_bit_t reserved3[0x00003]; 00797 pseudo_bit_t st[0x00004]; /* Transport Service Type: RC: 0, UC: 1, RD: 2, UD: 3, FCMND:4, FEXCH:5, SRC:6, MLX 7, Raw Eth 11 */ 00798 pseudo_bit_t reserved4[0x00008]; 00799 pseudo_bit_t state[0x00004]; /* QP/EE state: 00800 0 - RST 00801 1 - INIT 00802 2 - RTR 00803 3 - RTS 00804 4 - SQEr 00805 5 - SQD (Send Queue Drained) 00806 6 - ERR 00807 7 - Send Queue Draining 00808 8 - Reserved 00809 9 - Suspended 00810 A- F - Reserved 00811 (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ 00812 /* -------------- */ 00813 pseudo_bit_t pd[0x00018]; 00814 pseudo_bit_t reserved5[0x00008]; 00815 /* -------------- */ 00816 pseudo_bit_t reserved6[0x00004]; 00817 pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ 00818 pseudo_bit_t reserved7[0x00003]; 00819 pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. 00820 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 00821 pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ 00822 pseudo_bit_t reserved8[0x00001]; 00823 pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. 00824 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 00825 pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ 00826 pseudo_bit_t reserved9[0x00001]; 00827 pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. 00828 Must be equal to MTU for UD and MLX QPs. */ 00829 pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): 00830 0x1 - 256 bytes 00831 0x2 - 512 00832 0x3 - 1024 00833 0x4 - 2048 00834 other - reserved 00835 00836 Should be configured to 0x4 for UD and MLX QPs. */ 00837 /* -------------- */ 00838 pseudo_bit_t usr_page[0x00018]; /* UAR number to ring doorbells for this QP (aliased to doorbell and Blue Flame pages) */ 00839 pseudo_bit_t reserved10[0x00008]; 00840 /* -------------- */ 00841 pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained 00842 This field is valid for QUERY and ERR2RST commands only. */ 00843 pseudo_bit_t reserved11[0x00008]; 00844 /* -------------- */ 00845 pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ 00846 pseudo_bit_t reserved12[0x00008]; 00847 /* -------------- */ 00848 struct hermonprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ 00849 /* -------------- */ 00850 struct hermonprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ 00851 /* -------------- */ 00852 pseudo_bit_t reserved13[0x00003]; 00853 pseudo_bit_t reserved14[0x00001]; 00854 pseudo_bit_t reserved15[0x00001]; 00855 pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). 00856 The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ 00857 pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). 00858 The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ 00859 pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ 00860 pseudo_bit_t reserved16[0x00001]; 00861 pseudo_bit_t rnr_retry[0x00003]; 00862 pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ 00863 pseudo_bit_t reserved17[0x00002]; 00864 pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ 00865 pseudo_bit_t reserved18[0x00004]; 00866 pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ 00867 /* -------------- */ 00868 pseudo_bit_t reserved19[0x00020]; 00869 /* -------------- */ 00870 pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ 00871 pseudo_bit_t reserved20[0x00008]; 00872 /* -------------- */ 00873 pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ 00874 pseudo_bit_t reserved21[0x00008]; 00875 /* -------------- */ 00876 pseudo_bit_t reserved22[0x00040]; 00877 /* -------------- */ 00878 pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ 00879 pseudo_bit_t reserved23[0x00008]; 00880 /* -------------- */ 00881 pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ 00882 pseudo_bit_t reserved24[0x00008]; 00883 /* -------------- */ 00884 pseudo_bit_t reserved25[0x00004]; 00885 pseudo_bit_t ric[0x00001]; /* Invalid Credits. 00886 1 - place "Invalid Credits" to ACKs sent from this queue. 00887 0 - ACKs report the actual number of end to end credits on the connection. 00888 Not valid (reserved) in EE context. 00889 Must be set to 1 on QPs which are attached to SRQ. */ 00890 pseudo_bit_t reserved26[0x00001]; 00891 pseudo_bit_t page_offset[0x00006]; /* start address of wqes in first page (11:6), bits [5:0] reserved */ 00892 pseudo_bit_t reserved27[0x00001]; 00893 pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ 00894 pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ 00895 pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ 00896 pseudo_bit_t reserved28[0x00005]; 00897 pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. 00898 Must be 0 for EE context. */ 00899 pseudo_bit_t reserved29[0x00008]; 00900 /* -------------- */ 00901 pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ 00902 pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). 00903 Not valid (reserved) in EE context. */ 00904 pseudo_bit_t reserved30[0x00003]; 00905 /* -------------- */ 00906 pseudo_bit_t srcd[0x00010]; /* Scalable Reliable Connection Domain. Valid for SRC transport service */ 00907 pseudo_bit_t reserved31[0x00010]; 00908 /* -------------- */ 00909 pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ 00910 pseudo_bit_t reserved32[0x00008]; 00911 /* -------------- */ 00912 pseudo_bit_t db_record_addr_h[0x00020];/* QP DB Record physical address */ 00913 /* -------------- */ 00914 pseudo_bit_t reserved33[0x00002]; 00915 pseudo_bit_t db_record_addr_l[0x0001e];/* QP DB Record physical address */ 00916 /* -------------- */ 00917 pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. 00918 On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. 00919 Not valid (reserved) in EE context. */ 00920 /* -------------- */ 00921 pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. 00922 SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ 00923 pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ 00924 pseudo_bit_t reserved34[0x00007]; 00925 /* -------------- */ 00926 pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ 00927 pseudo_bit_t reserved35[0x00008]; 00928 /* -------------- */ 00929 pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 00930 Must be 0x0 in SQ initialization. 00931 (QUERY_QPEE only). */ 00932 pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. 00933 Must be 0x0 in RQ initialization. 00934 (QUERY_QPEE only). */ 00935 /* -------------- */ 00936 pseudo_bit_t reserved36[0x00040]; 00937 /* -------------- */ 00938 pseudo_bit_t rmc_parent_qpn[0x00018];/* reliable multicast parent queue number */ 00939 pseudo_bit_t hs[0x00001]; /* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */ 00940 pseudo_bit_t is[0x00001]; /* when set - inline scatter is enabled for this RQ */ 00941 pseudo_bit_t reserved37[0x00001]; 00942 pseudo_bit_t rme[0x00002]; /* Reliable Multicast 00943 00 - disabled 00944 01 - parent QP (requester) 00945 10 - child QP (requester) 00946 11 - responder QP 00947 Note that Reliable Multicast is a preliminary definition which can be subject to change. */ 00948 pseudo_bit_t reserved38[0x00002]; 00949 pseudo_bit_t mkey_rmp[0x00001]; /* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */ 00950 /* -------------- */ 00951 pseudo_bit_t base_mkey[0x00018]; /* Base Mkey bits [31:8]. Lower 8 bits must be zero. */ 00952 pseudo_bit_t num_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */ 00953 /* -------------- */ 00954 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 00955 pseudo_bit_t reserved39[0x00010]; 00956 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 00957 pseudo_bit_t reserved40[0x00002]; 00958 /* -------------- */ 00959 pseudo_bit_t reserved41[0x00003]; 00960 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 00961 /* -------------- */ 00962 pseudo_bit_t vft_lan[0x0000c]; 00963 pseudo_bit_t vft_prio[0x00003]; /* The Priority filed in the VFT header for FCP */ 00964 pseudo_bit_t reserved42[0x00001]; 00965 pseudo_bit_t cs_ctl[0x00009]; /* The Priority filed in the VFT header for FCP */ 00966 pseudo_bit_t reserved43[0x00006]; 00967 pseudo_bit_t ve[0x00001]; /* Should we add/check the VFT header */ 00968 /* -------------- */ 00969 pseudo_bit_t exch_base[0x00010]; /* For init QP only - The base exchanges */ 00970 pseudo_bit_t reserved44[0x00008]; 00971 pseudo_bit_t exch_size[0x00004]; /* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */ 00972 pseudo_bit_t reserved45[0x00003]; 00973 pseudo_bit_t fc[0x00001]; /* When set it mean that this QP is used for FIBRE CHANNEL. */ 00974 /* -------------- */ 00975 pseudo_bit_t remote_id[0x00018]; /* Peer NX port ID */ 00976 pseudo_bit_t reserved46[0x00008]; 00977 /* -------------- */ 00978 pseudo_bit_t fcp_mtu[0x0000a]; /* In 4*Bytes units. The MTU Size */ 00979 pseudo_bit_t reserved47[0x00006]; 00980 pseudo_bit_t my_id_indx[0x00008]; /* Index to My NX port ID table */ 00981 pseudo_bit_t vft_hop_count[0x00008];/* HopCnt value for the VFT header */ 00982 /* -------------- */ 00983 pseudo_bit_t reserved48[0x000c0]; 00984 /* -------------- */ 00985 }; 00986 00987 /* */ 00988 00989 struct hermonprm_mcg_qp_dw_st { /* Little Endian */ 00990 pseudo_bit_t qpn[0x00018]; 00991 pseudo_bit_t reserved0[0x00006]; 00992 pseudo_bit_t blck_lb[0x00001]; 00993 pseudo_bit_t reserved1[0x00001]; 00994 /* -------------- */ 00995 }; 00996 00997 /* Clear Interrupt [63:0] #### michal - match to PRM */ 00998 00999 struct hermonprm_clr_int_st { /* Little Endian */ 01000 pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] 01001 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 01002 This register is write-only. Reading from this register will cause undefined result 01003 */ 01004 /* -------------- */ 01005 pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] 01006 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 01007 This register is write-only. Reading from this register will cause undefined result */ 01008 /* -------------- */ 01009 }; 01010 01011 /* EQ Set CI DBs Table */ 01012 01013 struct hermonprm_eq_set_ci_table_st { /* Little Endian */ 01014 pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ 01015 /* -------------- */ 01016 pseudo_bit_t reserved0[0x00020]; 01017 /* -------------- */ 01018 pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ 01019 /* -------------- */ 01020 pseudo_bit_t reserved1[0x00020]; 01021 /* -------------- */ 01022 pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ 01023 /* -------------- */ 01024 pseudo_bit_t reserved2[0x00020]; 01025 /* -------------- */ 01026 pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ 01027 /* -------------- */ 01028 pseudo_bit_t reserved3[0x00020]; 01029 /* -------------- */ 01030 pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ 01031 /* -------------- */ 01032 pseudo_bit_t reserved4[0x00020]; 01033 /* -------------- */ 01034 pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ 01035 /* -------------- */ 01036 pseudo_bit_t reserved5[0x00020]; 01037 /* -------------- */ 01038 pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ 01039 /* -------------- */ 01040 pseudo_bit_t reserved6[0x00020]; 01041 /* -------------- */ 01042 pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ 01043 /* -------------- */ 01044 pseudo_bit_t reserved7[0x00020]; 01045 /* -------------- */ 01046 pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ 01047 /* -------------- */ 01048 pseudo_bit_t reserved8[0x00020]; 01049 /* -------------- */ 01050 pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ 01051 /* -------------- */ 01052 pseudo_bit_t reserved9[0x00020]; 01053 /* -------------- */ 01054 pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ 01055 /* -------------- */ 01056 pseudo_bit_t reserved10[0x00020]; 01057 /* -------------- */ 01058 pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ 01059 /* -------------- */ 01060 pseudo_bit_t reserved11[0x00020]; 01061 /* -------------- */ 01062 pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ 01063 /* -------------- */ 01064 pseudo_bit_t reserved12[0x00020]; 01065 /* -------------- */ 01066 pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ 01067 /* -------------- */ 01068 pseudo_bit_t reserved13[0x00020]; 01069 /* -------------- */ 01070 pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ 01071 /* -------------- */ 01072 pseudo_bit_t reserved14[0x00020]; 01073 /* -------------- */ 01074 pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ 01075 /* -------------- */ 01076 pseudo_bit_t reserved15[0x00020]; 01077 /* -------------- */ 01078 pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ 01079 /* -------------- */ 01080 pseudo_bit_t reserved16[0x00020]; 01081 /* -------------- */ 01082 pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ 01083 /* -------------- */ 01084 pseudo_bit_t reserved17[0x00020]; 01085 /* -------------- */ 01086 pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ 01087 /* -------------- */ 01088 pseudo_bit_t reserved18[0x00020]; 01089 /* -------------- */ 01090 pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ 01091 /* -------------- */ 01092 pseudo_bit_t reserved19[0x00020]; 01093 /* -------------- */ 01094 pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ 01095 /* -------------- */ 01096 pseudo_bit_t reserved20[0x00020]; 01097 /* -------------- */ 01098 pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ 01099 /* -------------- */ 01100 pseudo_bit_t reserved21[0x00020]; 01101 /* -------------- */ 01102 pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ 01103 /* -------------- */ 01104 pseudo_bit_t reserved22[0x00020]; 01105 /* -------------- */ 01106 pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ 01107 /* -------------- */ 01108 pseudo_bit_t reserved23[0x00020]; 01109 /* -------------- */ 01110 pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ 01111 /* -------------- */ 01112 pseudo_bit_t reserved24[0x00020]; 01113 /* -------------- */ 01114 pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ 01115 /* -------------- */ 01116 pseudo_bit_t reserved25[0x00020]; 01117 /* -------------- */ 01118 pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ 01119 /* -------------- */ 01120 pseudo_bit_t reserved26[0x00020]; 01121 /* -------------- */ 01122 pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ 01123 /* -------------- */ 01124 pseudo_bit_t reserved27[0x00020]; 01125 /* -------------- */ 01126 pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ 01127 /* -------------- */ 01128 pseudo_bit_t reserved28[0x00020]; 01129 /* -------------- */ 01130 pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ 01131 /* -------------- */ 01132 pseudo_bit_t reserved29[0x00020]; 01133 /* -------------- */ 01134 pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ 01135 /* -------------- */ 01136 pseudo_bit_t reserved30[0x00020]; 01137 /* -------------- */ 01138 pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ 01139 /* -------------- */ 01140 pseudo_bit_t reserved31[0x00020]; 01141 /* -------------- */ 01142 pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ 01143 /* -------------- */ 01144 pseudo_bit_t reserved32[0x00020]; 01145 /* -------------- */ 01146 pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ 01147 /* -------------- */ 01148 pseudo_bit_t reserved33[0x00020]; 01149 /* -------------- */ 01150 pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ 01151 /* -------------- */ 01152 pseudo_bit_t reserved34[0x00020]; 01153 /* -------------- */ 01154 pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ 01155 /* -------------- */ 01156 pseudo_bit_t reserved35[0x00020]; 01157 /* -------------- */ 01158 pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ 01159 /* -------------- */ 01160 pseudo_bit_t reserved36[0x00020]; 01161 /* -------------- */ 01162 pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ 01163 /* -------------- */ 01164 pseudo_bit_t reserved37[0x00020]; 01165 /* -------------- */ 01166 pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ 01167 /* -------------- */ 01168 pseudo_bit_t reserved38[0x00020]; 01169 /* -------------- */ 01170 pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ 01171 /* -------------- */ 01172 pseudo_bit_t reserved39[0x00020]; 01173 /* -------------- */ 01174 pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ 01175 /* -------------- */ 01176 pseudo_bit_t reserved40[0x00020]; 01177 /* -------------- */ 01178 pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ 01179 /* -------------- */ 01180 pseudo_bit_t reserved41[0x00020]; 01181 /* -------------- */ 01182 pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ 01183 /* -------------- */ 01184 pseudo_bit_t reserved42[0x00020]; 01185 /* -------------- */ 01186 pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ 01187 /* -------------- */ 01188 pseudo_bit_t reserved43[0x00020]; 01189 /* -------------- */ 01190 pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ 01191 /* -------------- */ 01192 pseudo_bit_t reserved44[0x00020]; 01193 /* -------------- */ 01194 pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ 01195 /* -------------- */ 01196 pseudo_bit_t reserved45[0x00020]; 01197 /* -------------- */ 01198 pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ 01199 /* -------------- */ 01200 pseudo_bit_t reserved46[0x00020]; 01201 /* -------------- */ 01202 pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ 01203 /* -------------- */ 01204 pseudo_bit_t reserved47[0x00020]; 01205 /* -------------- */ 01206 pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ 01207 /* -------------- */ 01208 pseudo_bit_t reserved48[0x00020]; 01209 /* -------------- */ 01210 pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ 01211 /* -------------- */ 01212 pseudo_bit_t reserved49[0x00020]; 01213 /* -------------- */ 01214 pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ 01215 /* -------------- */ 01216 pseudo_bit_t reserved50[0x00020]; 01217 /* -------------- */ 01218 pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ 01219 /* -------------- */ 01220 pseudo_bit_t reserved51[0x00020]; 01221 /* -------------- */ 01222 pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ 01223 /* -------------- */ 01224 pseudo_bit_t reserved52[0x00020]; 01225 /* -------------- */ 01226 pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ 01227 /* -------------- */ 01228 pseudo_bit_t reserved53[0x00020]; 01229 /* -------------- */ 01230 pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ 01231 /* -------------- */ 01232 pseudo_bit_t reserved54[0x00020]; 01233 /* -------------- */ 01234 pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ 01235 /* -------------- */ 01236 pseudo_bit_t reserved55[0x00020]; 01237 /* -------------- */ 01238 pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ 01239 /* -------------- */ 01240 pseudo_bit_t reserved56[0x00020]; 01241 /* -------------- */ 01242 pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ 01243 /* -------------- */ 01244 pseudo_bit_t reserved57[0x00020]; 01245 /* -------------- */ 01246 pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ 01247 /* -------------- */ 01248 pseudo_bit_t reserved58[0x00020]; 01249 /* -------------- */ 01250 pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ 01251 /* -------------- */ 01252 pseudo_bit_t reserved59[0x00020]; 01253 /* -------------- */ 01254 pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ 01255 /* -------------- */ 01256 pseudo_bit_t reserved60[0x00020]; 01257 /* -------------- */ 01258 pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ 01259 /* -------------- */ 01260 pseudo_bit_t reserved61[0x00020]; 01261 /* -------------- */ 01262 pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ 01263 /* -------------- */ 01264 pseudo_bit_t reserved62[0x00020]; 01265 /* -------------- */ 01266 pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ 01267 /* -------------- */ 01268 pseudo_bit_t reserved63[0x00020]; 01269 /* -------------- */ 01270 }; 01271 01272 /* InfiniHost-III-EX Configuration Registers #### michal - match to PRM */ 01273 01274 struct hermonprm_configuration_registers_st { /* Little Endian */ 01275 pseudo_bit_t reserved0[0x403400]; 01276 /* -------------- */ 01277 struct hermonprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ 01278 /* -------------- */ 01279 pseudo_bit_t reserved1[0x3fcb20]; 01280 /* -------------- */ 01281 }; 01282 01283 /* QP_DB_Record ### michal = gdror fixed */ 01284 01285 struct hermonprm_qp_db_record_st { /* Little Endian */ 01286 pseudo_bit_t receive_wqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ 01287 pseudo_bit_t reserved0[0x00010]; 01288 /* -------------- */ 01289 }; 01290 01291 /* CQ_ARM_DB_Record */ 01292 01293 struct hermonprm_cq_arm_db_record_st { /* Little Endian */ 01294 pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ 01295 /* -------------- */ 01296 pseudo_bit_t cmd[0x00003]; /* 0x0 - No command 01297 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. 01298 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. 01299 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated 01300 Other - Reserved */ 01301 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ 01302 pseudo_bit_t res[0x00003]; /* Must be 0x2 */ 01303 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 01304 /* -------------- */ 01305 }; 01306 01307 /* CQ_CI_DB_Record */ 01308 01309 struct hermonprm_cq_ci_db_record_st { /* Little Endian */ 01310 pseudo_bit_t counter[0x00020]; /* CQ counter */ 01311 /* -------------- */ 01312 pseudo_bit_t reserved0[0x00005]; 01313 pseudo_bit_t res[0x00003]; /* Must be 0x1 */ 01314 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 01315 /* -------------- */ 01316 }; 01317 01318 /* Virtual_Physical_Mapping */ 01319 01320 struct hermonprm_virtual_physical_mapping_st { /* Little Endian */ 01321 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ 01322 /* -------------- */ 01323 pseudo_bit_t reserved0[0x0000c]; 01324 pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ 01325 /* -------------- */ 01326 pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ 01327 /* -------------- */ 01328 pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ 01329 pseudo_bit_t reserved1[0x00006]; 01330 pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ 01331 /* -------------- */ 01332 }; 01333 01334 /* MOD_STAT_CFG #### michal - gdror fix */ 01335 01336 struct hermonprm_mod_stat_cfg_st { /* Little Endian */ 01337 pseudo_bit_t reserved0[0x00010]; 01338 pseudo_bit_t rx_options[0x00004]; /* number of RX options to sweep when doing SerDes parameters AutoNegotiation. */ 01339 pseudo_bit_t reserved1[0x00003]; 01340 pseudo_bit_t rx_options_m[0x00001]; /* Modify rx_options */ 01341 pseudo_bit_t tx_options[0x00004]; /* number of TX options to sweep when doing SerDes parameters AutoNegotiation. */ 01342 pseudo_bit_t reserved2[0x00003]; 01343 pseudo_bit_t tx_options_m[0x00001]; /* Modify tx_options */ 01344 /* -------------- */ 01345 pseudo_bit_t reserved3[0x00020]; 01346 /* -------------- */ 01347 pseudo_bit_t pre_amp[0x00004]; /* Pre Amplitude */ 01348 pseudo_bit_t pre_emp_pre_amp[0x00004]; 01349 pseudo_bit_t pre_emp_out[0x00004]; /* Pre Emphasis Out */ 01350 pseudo_bit_t voltage[0x00004]; 01351 pseudo_bit_t equ[0x00004]; /* Equalization */ 01352 pseudo_bit_t reserved4[0x0000b]; 01353 pseudo_bit_t serdes_m[0x00001]; /* Modify serdes parameters */ 01354 /* -------------- */ 01355 pseudo_bit_t lid[0x00010]; /* default LID */ 01356 pseudo_bit_t lid_m[0x00001]; /* Modify default LID */ 01357 pseudo_bit_t reserved5[0x00003]; 01358 pseudo_bit_t port_en[0x00001]; /* enable port (E_Key) */ 01359 pseudo_bit_t port_en_m[0x00001]; /* Modify port_en */ 01360 pseudo_bit_t reserved6[0x0000a]; 01361 /* -------------- */ 01362 pseudo_bit_t reserved7[0x0001f]; 01363 pseudo_bit_t guid_hi_m[0x00001]; /* Modify guid_hi */ 01364 /* -------------- */ 01365 pseudo_bit_t guid_hi[0x00020]; 01366 /* -------------- */ 01367 pseudo_bit_t reserved8[0x0001f]; 01368 pseudo_bit_t guid_lo_m[0x00001]; /* Modify guid_lo */ 01369 /* -------------- */ 01370 pseudo_bit_t guid_lo[0x00020]; 01371 /* -------------- */ 01372 pseudo_bit_t reserved9[0x0001f]; 01373 pseudo_bit_t nodeguid_hi_m[0x00001]; 01374 /* -------------- */ 01375 pseudo_bit_t nodeguid_hi[0x00020]; 01376 /* -------------- */ 01377 pseudo_bit_t reserved10[0x0001f]; 01378 pseudo_bit_t nodeguid_lo_m[0x00001]; 01379 /* -------------- */ 01380 pseudo_bit_t nodeguid_lo[0x00020]; 01381 /* -------------- */ 01382 pseudo_bit_t reserved11[0x00680]; 01383 /* -------------- */ 01384 }; 01385 01386 /* SRQ Context */ 01387 01388 struct hermonprm_srq_context_st { /* Little Endian */ 01389 pseudo_bit_t srqn[0x00018]; /* SRQ number */ 01390 pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. 01391 Maximum value is 0x10, i.e. 16M WQEs. */ 01392 pseudo_bit_t state[0x00004]; /* SRQ State: 01393 1111 - SW Ownership 01394 0000 - HW Ownership 01395 0001 - Error 01396 Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 01397 /* -------------- */ 01398 pseudo_bit_t src_domain[0x00010]; /* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */ 01399 pseudo_bit_t reserved0[0x00008]; 01400 pseudo_bit_t log_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ 01401 pseudo_bit_t reserved1[0x00005]; 01402 /* -------------- */ 01403 pseudo_bit_t cqn[0x00018]; /* Completion Queue to report SRC messages directed to this SRQ. */ 01404 pseudo_bit_t page_offset[0x00006]; /* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,“Work Queue Buffer Structure”) */ 01405 pseudo_bit_t reserved2[0x00002]; 01406 /* -------------- */ 01407 pseudo_bit_t reserved3[0x00020]; 01408 /* -------------- */ 01409 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 01410 pseudo_bit_t reserved4[0x00010]; 01411 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 01412 pseudo_bit_t reserved5[0x00002]; 01413 /* -------------- */ 01414 pseudo_bit_t reserved6[0x00003]; 01415 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 01416 /* -------------- */ 01417 pseudo_bit_t pd[0x00018]; /* SRQ protection domain */ 01418 pseudo_bit_t reserved7[0x00008]; 01419 /* -------------- */ 01420 pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 01421 pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 01422 /* -------------- */ 01423 pseudo_bit_t srq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */ 01424 pseudo_bit_t reserved8[0x00010]; 01425 /* -------------- */ 01426 pseudo_bit_t reserved9[0x00020]; 01427 /* -------------- */ 01428 pseudo_bit_t db_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */ 01429 /* -------------- */ 01430 pseudo_bit_t reserved10[0x00002]; 01431 pseudo_bit_t db_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */ 01432 /* -------------- */ 01433 }; 01434 01435 /* PBL */ 01436 01437 struct hermonprm_pbl_st { /* Little Endian */ 01438 pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ 01439 /* -------------- */ 01440 pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ 01441 /* -------------- */ 01442 pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ 01443 /* -------------- */ 01444 pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ 01445 /* -------------- */ 01446 pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ 01447 /* -------------- */ 01448 pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ 01449 /* -------------- */ 01450 pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ 01451 /* -------------- */ 01452 pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ 01453 /* -------------- */ 01454 }; 01455 01456 /* Performance Counters #### michal - gdror fixed */ 01457 01458 struct hermonprm_performance_counters_st { /* Little Endian */ 01459 pseudo_bit_t reserved0[0x00080]; 01460 /* -------------- */ 01461 pseudo_bit_t reserved1[0x00080]; 01462 /* -------------- */ 01463 pseudo_bit_t reserved2[0x00080]; 01464 /* -------------- */ 01465 pseudo_bit_t reserved3[0x00060]; 01466 /* -------------- */ 01467 pseudo_bit_t reserved4[0x00620]; 01468 /* -------------- */ 01469 }; 01470 01471 /* Transport and CI Error Counters */ 01472 01473 struct hermonprm_transport_and_ci_error_counters_st { /* Little Endian */ 01474 pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ 01475 /* -------------- */ 01476 pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ 01477 /* -------------- */ 01478 pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ 01479 /* -------------- */ 01480 pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ 01481 /* -------------- */ 01482 pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ 01483 /* -------------- */ 01484 pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ 01485 /* -------------- */ 01486 pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ 01487 /* -------------- */ 01488 pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ 01489 /* -------------- */ 01490 pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. 01491 Incremented each time a CQE with error is generated */ 01492 /* -------------- */ 01493 pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. 01494 Incremented each time a CQE with error is generated */ 01495 /* -------------- */ 01496 pseudo_bit_t reserved0[0x00020]; 01497 /* -------------- */ 01498 pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ 01499 /* -------------- */ 01500 pseudo_bit_t reserved1[0x00020]; 01501 /* -------------- */ 01502 pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ 01503 /* -------------- */ 01504 pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ 01505 /* -------------- */ 01506 pseudo_bit_t reserved2[0x00040]; 01507 /* -------------- */ 01508 pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors 01509 NAK-Invalid Request on: 01510 1. Unsupported OpCode: Responder detected an unsupported OpCode. 01511 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such 01512 as a missing "Last" packet. 01513 Note: there is no PSN error, thus this does not indicate a dropped packet. */ 01514 /* -------------- */ 01515 pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. 01516 NAK may or may not be sent. 01517 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): 01518 Inbound request OpCode was either reserved, or was for a function not supported by this 01519 QP. (E.g. RDMA or ATOMIC on QP not set up for this). 01520 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. 01521 3. Too many RDMA READ or ATOMIC Requests: There were more requests received 01522 and not ACKed than allowed for the connection. 01523 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder 01524 detected an error in the sequence of OpCodes; a missing "Last" packet 01525 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder 01526 detected an error in the sequence of OpCodes; a missing "First" packet 01527 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able 01528 buffer space. 01529 7. Length error: RDMA WRITE request message contained too much or too little pay-load 01530 data compared to the DMA length advertised in the first or only packet. 01531 8. Length error: Payload length was not consistent with the opcode: 01532 a: 0 byte <= "only" <= PMTU bytes 01533 b: ("first" or "middle") == PMTU bytes 01534 c: 1byte <= "last" <= PMTU bytes 01535 9. Length error: Inbound message exceeded the size supported by the CA port. */ 01536 /* -------------- */ 01537 pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. 01538 NAK-Remote Access Error on: 01539 R_Key Violation: Responder detected an invalid R_Key while executing an RDMA 01540 Request. */ 01541 /* -------------- */ 01542 pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. 01543 R_Key Violation Responder detected an R_Key violation while executing an RDMA 01544 request. 01545 NAK may or may not be sent. */ 01546 /* -------------- */ 01547 pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. 01548 NAK-Remote Operation Error on: 01549 Remote Operation Error: Responder encountered an error, (local to the responder), 01550 which prevented it from completing the request. */ 01551 /* -------------- */ 01552 pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. 01553 NAK-Remote Operation Error on: 01554 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing 01555 the packet. 01556 2. Remote Operation Error: Responder encountered an error, (local to the responder), 01557 which prevented it from completing the request. */ 01558 /* -------------- */ 01559 pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ 01560 /* -------------- */ 01561 pseudo_bit_t reserved3[0x00020]; 01562 /* -------------- */ 01563 pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ 01564 /* -------------- */ 01565 pseudo_bit_t rq_num_rnr[0x00020]; /* Responder - the number of RNR Naks sent */ 01566 /* -------------- */ 01567 pseudo_bit_t sq_num_rnr[0x00020]; /* Requester - the number of RNR Naks received */ 01568 /* -------------- */ 01569 pseudo_bit_t reserved4[0x00040]; 01570 /* -------------- */ 01571 pseudo_bit_t reserved5[0x00020]; 01572 /* -------------- */ 01573 pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ 01574 /* -------------- */ 01575 pseudo_bit_t reserved6[0x00020]; 01576 /* -------------- */ 01577 pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ 01578 /* -------------- */ 01579 pseudo_bit_t reserved7[0x00020]; 01580 /* -------------- */ 01581 pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ 01582 /* -------------- */ 01583 pseudo_bit_t reserved8[0x00380]; 01584 /* -------------- */ 01585 pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ 01586 /* -------------- */ 01587 pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ 01588 /* -------------- */ 01589 pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ 01590 /* -------------- */ 01591 pseudo_bit_t reserved9[0x00020]; 01592 /* -------------- */ 01593 pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ 01594 /* -------------- */ 01595 pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ 01596 /* -------------- */ 01597 pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ 01598 /* -------------- */ 01599 pseudo_bit_t reserved10[0x00020]; 01600 /* -------------- */ 01601 pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ 01602 /* -------------- */ 01603 pseudo_bit_t reserved11[0x003e0]; 01604 /* -------------- */ 01605 pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ 01606 /* -------------- */ 01607 pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ 01608 /* -------------- */ 01609 pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ 01610 /* -------------- */ 01611 pseudo_bit_t reserved12[0x002a0]; 01612 /* -------------- */ 01613 }; 01614 01615 /* Event_data Field - HCR Completion Event #### michal - match PRM */ 01616 01617 struct hermonprm_hcr_completion_event_st { /* Little Endian */ 01618 pseudo_bit_t token[0x00010]; /* HCR Token */ 01619 pseudo_bit_t reserved0[0x00010]; 01620 /* -------------- */ 01621 pseudo_bit_t reserved1[0x00020]; 01622 /* -------------- */ 01623 pseudo_bit_t status[0x00008]; /* HCR Status */ 01624 pseudo_bit_t reserved2[0x00018]; 01625 /* -------------- */ 01626 pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ 01627 /* -------------- */ 01628 pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ 01629 /* -------------- */ 01630 pseudo_bit_t reserved3[0x00020]; 01631 /* -------------- */ 01632 }; 01633 01634 /* Completion with Error CQE #### michal - gdror fixed */ 01635 01636 struct hermonprm_completion_with_error_st { /* Little Endian */ 01637 pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 01638 pseudo_bit_t reserved0[0x00008]; 01639 /* -------------- */ 01640 pseudo_bit_t reserved1[0x000a0]; 01641 /* -------------- */ 01642 pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: 01643 0x01 - Local Length Error 01644 0x02 - Local QP Operation Error 01645 0x03 - Local EE Context Operation Error 01646 0x04 - Local Protection Error 01647 0x05 - Work Request Flushed Error 01648 0x06 - Memory Window Bind Error 01649 0x10 - Bad Response Error 01650 0x11 - Local Access Error 01651 0x12 - Remote Invalid Request Error 01652 0x13 - Remote Access Error 01653 0x14 - Remote Operation Error 01654 0x15 - Transport Retry Counter Exceeded 01655 0x16 - RNR Retry Counter Exceeded 01656 0x20 - Local RDD Violation Error 01657 0x21 - Remote Invalid RD Request 01658 0x22 - Remote Aborted Error 01659 0x23 - Invalid EE Context Number 01660 0x24 - Invalid EE Context State 01661 other - Reserved 01662 Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ 01663 pseudo_bit_t vendor_error_syndrome[0x00008]; 01664 pseudo_bit_t wqe_counter[0x00010]; 01665 /* -------------- */ 01666 pseudo_bit_t opcode[0x00005]; /* The opcode of WQE completion is reported for. 01667 01668 The following values are reported in case of completion with error: 01669 0xFE - For completion with error on Receive Queues 01670 0xFF - For completion with error on Send Queues */ 01671 pseudo_bit_t reserved2[0x00001]; 01672 pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 01673 pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 01674 pseudo_bit_t reserved3[0x00018]; 01675 /* -------------- */ 01676 }; 01677 01678 /* Resize CQ Input Mailbox */ 01679 01680 struct hermonprm_resize_cq_st { /* Little Endian */ 01681 pseudo_bit_t reserved0[0x00040]; 01682 /* -------------- */ 01683 pseudo_bit_t reserved1[0x00006]; 01684 pseudo_bit_t page_offset[0x00006]; 01685 pseudo_bit_t reserved2[0x00014]; 01686 /* -------------- */ 01687 pseudo_bit_t reserved3[0x00018]; 01688 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ 01689 pseudo_bit_t reserved4[0x00003]; 01690 /* -------------- */ 01691 pseudo_bit_t reserved5[0x00020]; 01692 /* -------------- */ 01693 pseudo_bit_t mtt_base_addr_h[0x00008]; 01694 pseudo_bit_t reserved6[0x00010]; 01695 pseudo_bit_t log2_page_size[0x00006]; 01696 pseudo_bit_t reserved7[0x00002]; 01697 /* -------------- */ 01698 pseudo_bit_t reserved8[0x00003]; 01699 pseudo_bit_t mtt_base_addr_l[0x0001d]; 01700 /* -------------- */ 01701 pseudo_bit_t reserved9[0x00020]; 01702 /* -------------- */ 01703 pseudo_bit_t reserved10[0x00100]; 01704 /* -------------- */ 01705 }; 01706 01707 /* MAD_IFC Input Modifier */ 01708 01709 struct hermonprm_mad_ifc_input_modifier_st { /* Little Endian */ 01710 pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ 01711 pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. 01712 Required for trap generation when BKey check is enabled and for global routed packets. */ 01713 pseudo_bit_t reserved0[0x00007]; 01714 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 01715 This field is required for trap generation upon MKey/BKey validation. */ 01716 /* -------------- */ 01717 }; 01718 01719 /* MAD_IFC Input Mailbox ###michal -gdror fixed */ 01720 01721 struct hermonprm_mad_ifc_st { /* Little Endian */ 01722 pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ 01723 /* -------------- */ 01724 pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. 01725 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01726 pseudo_bit_t reserved0[0x00008]; 01727 /* -------------- */ 01728 pseudo_bit_t reserved1[0x00020]; 01729 /* -------------- */ 01730 pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. 01731 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01732 pseudo_bit_t reserved2[0x00008]; 01733 /* -------------- */ 01734 pseudo_bit_t reserved3[0x00010]; 01735 pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. 01736 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01737 pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. 01738 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01739 pseudo_bit_t reserved4[0x00004]; 01740 pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. 01741 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01742 /* -------------- */ 01743 pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. 01744 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01745 pseudo_bit_t reserved5[0x00010]; 01746 /* -------------- */ 01747 pseudo_bit_t reserved6[0x00160]; 01748 /* -------------- */ 01749 pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. 01750 Valid if Mad_extended_info bit (in the input modifier) and g bit are set. 01751 Otherwise this field is reserved. */ 01752 /* -------------- */ 01753 pseudo_bit_t reserved7[0x004c0]; 01754 /* -------------- */ 01755 }; 01756 01757 /* Query Debug Message #### michal - gdror fixed */ 01758 01759 struct hermonprm_query_debug_msg_st { /* Little Endian */ 01760 pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ 01761 /* -------------- */ 01762 pseudo_bit_t v[0x00001]; /* Physical translation is valid */ 01763 pseudo_bit_t reserved0[0x0000b]; 01764 pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ 01765 /* -------------- */ 01766 pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ 01767 /* -------------- */ 01768 pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ 01769 /* -------------- */ 01770 pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ 01771 /* -------------- */ 01772 pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ 01773 /* -------------- */ 01774 pseudo_bit_t reserved1[0x000c0]; 01775 /* -------------- */ 01776 pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ 01777 /* -------------- */ 01778 pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ 01779 /* -------------- */ 01780 pseudo_bit_t reserved2[0x00040]; 01781 /* -------------- */ 01782 pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ 01783 /* -------------- */ 01784 pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ 01785 /* -------------- */ 01786 pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ 01787 /* -------------- */ 01788 pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ 01789 /* -------------- */ 01790 pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ 01791 /* -------------- */ 01792 pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ 01793 /* -------------- */ 01794 pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ 01795 /* -------------- */ 01796 pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ 01797 /* -------------- */ 01798 pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ 01799 /* -------------- */ 01800 pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ 01801 /* -------------- */ 01802 pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ 01803 /* -------------- */ 01804 pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ 01805 /* -------------- */ 01806 pseudo_bit_t reserved3[0x00080]; 01807 /* -------------- */ 01808 pseudo_bit_t hw_buff_addr[0x00020]; /* Dror Mux Bohrer tracer */ 01809 /* -------------- */ 01810 pseudo_bit_t hw_buff_size[0x00020]; 01811 /* -------------- */ 01812 pseudo_bit_t reserved4[0x003c0]; 01813 /* -------------- */ 01814 }; 01815 01816 /* User Access Region */ 01817 01818 struct hermonprm_uar_st { /* Little Endian */ 01819 struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ 01820 /* -------------- */ 01821 struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 01822 /* -------------- */ 01823 pseudo_bit_t reserved0[0x00040]; 01824 /* -------------- */ 01825 struct hermonprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ 01826 /* -------------- */ 01827 pseudo_bit_t reserved1[0x03ec0]; 01828 /* -------------- */ 01829 }; 01830 01831 /* Receive doorbell */ 01832 01833 struct hermonprm_receive_doorbell_st { /* Little Endian */ 01834 pseudo_bit_t reserved0[0x00008]; 01835 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ 01836 pseudo_bit_t reserved1[0x00008]; 01837 /* -------------- */ 01838 pseudo_bit_t reserved2[0x00005]; 01839 pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ 01840 pseudo_bit_t reserved3[0x00002]; 01841 pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ 01842 /* -------------- */ 01843 }; 01844 01845 /* SET_IB Parameters */ 01846 01847 struct hermonprm_set_ib_st { /* Little Endian */ 01848 pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ 01849 pseudo_bit_t reserved0[0x00011]; 01850 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 01851 system_image_guid and sig must be the same for all ports. */ 01852 pseudo_bit_t reserved1[0x0000d]; 01853 /* -------------- */ 01854 pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ 01855 /* -------------- */ 01856 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 01857 Must be the same for both ports. */ 01858 /* -------------- */ 01859 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 01860 Must be the same for both ports. */ 01861 /* -------------- */ 01862 pseudo_bit_t reserved2[0x00180]; 01863 /* -------------- */ 01864 }; 01865 01866 /* Multicast Group Member #### michal - gdror fixed */ 01867 01868 struct hermonprm_mgm_entry_st { /* Little Endian */ 01869 pseudo_bit_t reserved0[0x00006]; 01870 pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. 01871 The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. 01872 next_gid_index=0 means end of the chain. */ 01873 /* -------------- */ 01874 pseudo_bit_t reserved1[0x00060]; 01875 /* -------------- */ 01876 pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. 01877 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01878 /* -------------- */ 01879 pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. 01880 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01881 /* -------------- */ 01882 pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. 01883 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01884 /* -------------- */ 01885 pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. 01886 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01887 /* -------------- */ 01888 struct hermonprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ 01889 /* -------------- */ 01890 struct hermonprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ 01891 /* -------------- */ 01892 struct hermonprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ 01893 /* -------------- */ 01894 struct hermonprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ 01895 /* -------------- */ 01896 struct hermonprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ 01897 /* -------------- */ 01898 struct hermonprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ 01899 /* -------------- */ 01900 struct hermonprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ 01901 /* -------------- */ 01902 struct hermonprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ 01903 /* -------------- */ 01904 }; 01905 01906 /* INIT_PORT Parameters #### michal - match PRM */ 01907 01908 struct hermonprm_init_port_st { /* Little Endian */ 01909 pseudo_bit_t reserved0[0x00004]; 01910 pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. 01911 Legal values are 1,2,4 and 8. */ 01912 pseudo_bit_t port_width_cap[0x00004];/* IB Port Width 01913 1 - 1x 01914 3 - 1x, 4x 01915 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) 01916 else - Reserved */ 01917 pseudo_bit_t reserved1[0x00004]; 01918 pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ 01919 pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. 01920 node_guid and ng must be the same for all ports. */ 01921 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 01922 system_image_guid and sig must be the same for all ports. */ 01923 pseudo_bit_t reserved2[0x0000d]; 01924 /* -------------- */ 01925 pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ 01926 pseudo_bit_t mtu[0x00010]; /* Maximum MTU Supported in bytes 01927 must be: 256, 512, 1024, 2048 or 4096 01928 For Eth port, can be any 01929 Field must not cross device capabilities as reported 01930 */ 01931 /* -------------- */ 01932 pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. 01933 Must be the same for both ports. */ 01934 pseudo_bit_t reserved3[0x00010]; 01935 /* -------------- */ 01936 pseudo_bit_t reserved4[0x00020]; 01937 /* -------------- */ 01938 pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ 01939 /* -------------- */ 01940 pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ 01941 /* -------------- */ 01942 pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set 01943 Must be the same for both ports. */ 01944 /* -------------- */ 01945 pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set 01946 Must be the same for both ports. */ 01947 /* -------------- */ 01948 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 01949 Must be the same for both ports. */ 01950 /* -------------- */ 01951 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 01952 Must be the same for both ports. */ 01953 /* -------------- */ 01954 pseudo_bit_t reserved5[0x006c0]; 01955 /* -------------- */ 01956 }; 01957 01958 /* Query Device Capablities #### michal - gdror fixed */ 01959 01960 struct hermonprm_query_dev_cap_st { /* Little Endian */ 01961 pseudo_bit_t reserved0[0x00080]; 01962 /* -------------- */ 01963 pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ 01964 pseudo_bit_t reserved1[0x00003]; 01965 pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use 01966 The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ 01967 pseudo_bit_t reserved2[0x00004]; 01968 pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ 01969 pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ 01970 /* -------------- */ 01971 pseudo_bit_t log_max_scqs[0x00004]; /* log base 2 of number of supported schedule queues */ 01972 pseudo_bit_t reserved3[0x00004]; 01973 pseudo_bit_t num_rsvd_scqs[0x00006]; 01974 pseudo_bit_t reserved4[0x00002]; 01975 pseudo_bit_t log_max_srqs[0x00005]; 01976 pseudo_bit_t reserved5[0x00007]; 01977 pseudo_bit_t log2_rsvd_srqs[0x00004]; 01978 /* -------------- */ 01979 pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ 01980 pseudo_bit_t reserved6[0x00003]; 01981 pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use 01982 The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ 01983 pseudo_bit_t reserved7[0x00004]; 01984 pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ 01985 pseudo_bit_t reserved8[0x00008]; 01986 /* -------------- */ 01987 pseudo_bit_t log_max_eq[0x00004]; /* Log2 of the Maximum number of EQs */ 01988 pseudo_bit_t reserved9[0x00004]; 01989 pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use 01990 The reserved resources are numbered from 0 to num_rsvd_eqs-1 01991 If 0 - no resources are reserved. */ 01992 pseudo_bit_t reserved10[0x00004]; 01993 pseudo_bit_t log_max_d_mpts[0x00006];/* Log (base 2) of the maximum number of data MPT entries (the number of Regions/Windows) */ 01994 pseudo_bit_t reserved11[0x00002]; 01995 pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ 01996 /* -------------- */ 01997 pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ 01998 pseudo_bit_t reserved12[0x00002]; 01999 pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use 02000 The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ 02001 pseudo_bit_t reserved13[0x00004]; 02002 pseudo_bit_t log_max_mrw_sz[0x00007];/* Log2 of the Maximum Size of Memory Region/Window. is it in PRM layout? */ 02003 pseudo_bit_t reserved14[0x00005]; 02004 pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use 02005 The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 02006 */ 02007 /* -------------- */ 02008 pseudo_bit_t reserved15[0x00020]; 02009 /* -------------- */ 02010 pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ 02011 pseudo_bit_t reserved16[0x0000a]; 02012 pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ 02013 pseudo_bit_t reserved17[0x0000a]; 02014 /* -------------- */ 02015 pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ 02016 pseudo_bit_t reserved18[0x0001a]; 02017 /* -------------- */ 02018 pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ 02019 pseudo_bit_t reserved19[0x0001f]; 02020 /* -------------- */ 02021 pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ 02022 pseudo_bit_t max_vl_ib[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */ 02023 pseudo_bit_t ib_port_width[0x00004];/* IB Port Width 02024 1 - 1x 02025 3 - 1x, 4x 02026 11 - 1x, 4x or 12x 02027 else - Reserved */ 02028 pseudo_bit_t ib_mtu[0x00004]; /* Maximum MTU Supported 02029 0x0 - Reserved 02030 0x1 - 256 02031 0x2 - 512 02032 0x3 - 1024 02033 0x4 - 2048 02034 0x5 - 4096 02035 0x6-0xF Reserved */ 02036 pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. 02037 The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ 02038 pseudo_bit_t port_type[0x00004]; /* Hermon New. bit per port. bit0 is first port. value '1' is ehternet. '0' is IB */ 02039 pseudo_bit_t reserved20[0x00004]; 02040 pseudo_bit_t w[0x00001]; /* Hermon New. 10GB eth support */ 02041 pseudo_bit_t j[0x00001]; /* Hermon New. Jumbo frame support */ 02042 pseudo_bit_t reserved21[0x00001]; 02043 /* -------------- */ 02044 pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ 02045 pseudo_bit_t reserved22[0x00004]; 02046 pseudo_bit_t log_ethtype[0x00004]; /* Hermon New. log2 eth type table size */ 02047 pseudo_bit_t reserved23[0x00004]; 02048 pseudo_bit_t log_drain_size[0x00008];/* Log (base 2) of minimum size of the NoDropVLDrain buffer, specified in 4Kpages units */ 02049 pseudo_bit_t log_max_msg[0x00005]; /* Log (base 2) of the maximum message size supported by the device */ 02050 pseudo_bit_t reserved24[0x00003]; 02051 /* -------------- */ 02052 pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ 02053 pseudo_bit_t reserved25[0x0000c]; 02054 pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported 02055 bit 0 - full bw 02056 bit 1 - 1/4 bw 02057 bit 2 - 1/8 bw 02058 bit 3 - 1/2 bw; */ 02059 /* -------------- */ 02060 pseudo_bit_t reserved26[0x00020]; 02061 /* -------------- */ 02062 pseudo_bit_t rc[0x00001]; /* RC Transport supported */ 02063 pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ 02064 pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ 02065 pseudo_bit_t src[0x00001]; /* SRC Transport Supported. Hermon New instead of RD. */ 02066 pseudo_bit_t rcm[0x00001]; /* Reliable Multicast support. Hermon New instead of IPv6 Transport Supported */ 02067 pseudo_bit_t fcoib[0x00001]; /* Hermon New */ 02068 pseudo_bit_t srq[0x00001]; /* SRQ is supported 02069 */ 02070 pseudo_bit_t checksum[0x00001]; /* IP over IB checksum is supported */ 02071 pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ 02072 pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ 02073 pseudo_bit_t vmm[0x00001]; /* Hermon New */ 02074 pseudo_bit_t fcoe[0x00001]; 02075 pseudo_bit_t dpdp[0x00001]; /* Dual Port Different Protocols */ 02076 pseudo_bit_t raw_ethertype[0x00001]; 02077 pseudo_bit_t raw_ipv6[0x00001]; 02078 pseudo_bit_t blh[0x00001]; 02079 pseudo_bit_t mw[0x00001]; /* Memory windows supported */ 02080 pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ 02081 pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ 02082 pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ 02083 pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ 02084 pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ 02085 pseudo_bit_t reserved28[0x00002]; 02086 pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ 02087 pseudo_bit_t r[0x00001]; /* Router mode supported */ 02088 pseudo_bit_t reserved29[0x00006]; 02089 /* -------------- */ 02090 pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). 02091 For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ 02092 pseudo_bit_t reserved30[0x00008]; 02093 pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ 02094 pseudo_bit_t reserved31[0x00006]; 02095 pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use 02096 The reserved resources are numbered from 0 to num_reserved_uars-1 02097 Note that UAR number num_reserved_uars is always for the kernel. */ 02098 /* -------------- */ 02099 pseudo_bit_t log_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */ 02100 pseudo_bit_t reserved32[0x00002]; 02101 pseudo_bit_t log_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */ 02102 pseudo_bit_t reserved33[0x00002]; 02103 pseudo_bit_t log_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */ 02104 pseudo_bit_t reserved34[0x0000a]; 02105 pseudo_bit_t bf[0x00001]; /* If set to "1" then BlueFlame may be used. */ 02106 /* -------------- */ 02107 pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ 02108 pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ 02109 pseudo_bit_t reserved35[0x00008]; 02110 /* -------------- */ 02111 pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ 02112 pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ 02113 pseudo_bit_t reserved36[0x00008]; 02114 /* -------------- */ 02115 pseudo_bit_t reserved37[0x00001]; 02116 pseudo_bit_t fexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */ 02117 pseudo_bit_t fcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */ 02118 pseudo_bit_t fexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */ 02119 /* -------------- */ 02120 pseudo_bit_t reserved38[0x00020]; 02121 /* -------------- */ 02122 pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ 02123 pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. 02124 The reserved resources are numbered from 0 to num_reserved_mcgs-1 02125 If 0 - no resources are reserved. */ 02126 pseudo_bit_t reserved39[0x00004]; 02127 pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ 02128 pseudo_bit_t reserved40[0x00008]; 02129 /* -------------- */ 02130 pseudo_bit_t log_max_srcds[0x00004];/* Log2 of the maximum number of SRC Domains */ 02131 pseudo_bit_t reserved41[0x00008]; 02132 pseudo_bit_t num_rsvd_scrds[0x00004];/* The number of SRCDs reserved for firmware use 02133 The reserved resources are numbered from 0 to num_reserved_rdds-1. 02134 If 0 - no resources are reserved. */ 02135 pseudo_bit_t log_max_pd[0x00005]; /* Log2 of the maximum number of PDs */ 02136 pseudo_bit_t reserved42[0x00007]; 02137 pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use 02138 The reserved resources are numbered from 0 to num_reserved_pds-1 02139 If 0 - no resources are reserved. */ 02140 /* -------------- */ 02141 pseudo_bit_t reserved43[0x000c0]; 02142 /* -------------- */ 02143 pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device 02144 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 02145 pseudo_bit_t rdmardc_entry_sz[0x00010];/* RdmaRdC Entry Size for the device 02146 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 02147 /* -------------- */ 02148 pseudo_bit_t altc_entry_sz[0x00010];/* Extended QPC entry size for the device 02149 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02150 pseudo_bit_t aux_entry_sz[0x00010]; /* Auxilary context entry size */ 02151 /* -------------- */ 02152 pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device 02153 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02154 pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device 02155 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02156 /* -------------- */ 02157 pseudo_bit_t c_mpt_entry_sz[0x00010];/* cMPT entry size in Bytes for the device. 02158 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02159 pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device 02160 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02161 /* -------------- */ 02162 pseudo_bit_t d_mpt_entry_sz[0x00010];/* dMPT entry size in Bytes for the device. 02163 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02164 pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. 02165 For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ 02166 /* -------------- */ 02167 pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ 02168 pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: 02169 0 - Type 2A - QP Number Association; or 02170 1 - Type 2B - QP Number and PD Association. */ 02171 pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ 02172 pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. */ 02173 pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ 02174 pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ 02175 pseudo_bit_t reserved44[0x0001a]; 02176 /* -------------- */ 02177 pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ 02178 /* -------------- */ 02179 pseudo_bit_t reserved45[0x00020]; 02180 /* -------------- */ 02181 pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ 02182 /* -------------- */ 02183 pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ 02184 /* -------------- */ 02185 pseudo_bit_t reserved46[0x002c0]; 02186 /* -------------- */ 02187 }; 02188 02189 /* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */ 02190 02191 struct hermonprm_query_adapter_st { /* Little Endian */ 02192 pseudo_bit_t reserved0[0x00080]; 02193 /* -------------- */ 02194 pseudo_bit_t reserved1[0x00018]; 02195 pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ 02196 /* -------------- */ 02197 pseudo_bit_t reserved2[0x00060]; 02198 /* -------------- */ 02199 struct hermonprm_vsd_st vsd; /* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */ 02200 /* -------------- */ 02201 }; 02202 02203 /* QUERY_FW Parameters Block #### michal - doesn't match PRM */ 02204 02205 struct hermonprm_query_fw_st { /* Little Endian */ 02206 pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ 02207 pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ 02208 /* -------------- */ 02209 pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ 02210 pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ 02211 /* -------------- */ 02212 pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ 02213 pseudo_bit_t reserved0[0x00010]; 02214 /* -------------- */ 02215 pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ 02216 pseudo_bit_t reserved1[0x00017]; 02217 pseudo_bit_t dt[0x00001]; /* Debug Trace Support 02218 0 - Debug trace is not supported 02219 1 - Debug trace is supported */ 02220 /* -------------- */ 02221 pseudo_bit_t reserved2[0x00001]; 02222 pseudo_bit_t ccq[0x00001]; /* CCQ support */ 02223 pseudo_bit_t reserved3[0x00006]; 02224 pseudo_bit_t fw_seconds[0x00008]; /* FW timestamp - seconds. Dispalyed as Hexadecimal number */ 02225 pseudo_bit_t fw_minutes[0x00008]; /* FW timestamp - minutes. Dispalyed as Hexadecimal number */ 02226 pseudo_bit_t fw_hour[0x00008]; /* FW timestamp - hour. Dispalyed as Hexadecimal number */ 02227 /* -------------- */ 02228 pseudo_bit_t fw_day[0x00008]; /* FW timestamp - day. Dispalyed as Hexadecimal number */ 02229 pseudo_bit_t fw_month[0x00008]; /* FW timestamp - month. Dispalyed as Hexadecimal number */ 02230 pseudo_bit_t fw_year[0x00010]; /* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */ 02231 /* -------------- */ 02232 pseudo_bit_t reserved4[0x00040]; 02233 /* -------------- */ 02234 pseudo_bit_t clr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 02235 /* -------------- */ 02236 pseudo_bit_t clr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registerÂ’s offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 02237 /* -------------- */ 02238 pseudo_bit_t reserved5[0x0001e]; 02239 pseudo_bit_t clr_int_bar[0x00002]; /* PCI base address register (BAR) where clr_int register is located. 02240 00 - BAR 0-1 02241 01 - BAR 2-3 02242 10 - BAR 4-5 02243 11 - Reserved 02244 The PCI BARs of ConnectX are 64 bit BARs. 02245 In ConnectX, clr_int register is located on BAR 0-1. */ 02246 /* -------------- */ 02247 pseudo_bit_t reserved6[0x00020]; 02248 /* -------------- */ 02249 pseudo_bit_t error_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */ 02250 /* -------------- */ 02251 pseudo_bit_t error_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */ 02252 /* -------------- */ 02253 pseudo_bit_t error_buf_size[0x00020];/* Size in words */ 02254 /* -------------- */ 02255 pseudo_bit_t reserved7[0x0001e]; 02256 pseudo_bit_t error_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located. 02257 00 - BAR 0-1 02258 01 - BAR 2-3 02259 10 - BAR 4-5 02260 11 - Reserved 02261 The PCI BARs of ConnectX are 64 bit BARs. 02262 In ConnectX, error_buf register is located on BAR 0-1. */ 02263 /* -------------- */ 02264 pseudo_bit_t reserved8[0x00600]; 02265 /* -------------- */ 02266 }; 02267 02268 /* Memory Access Parameters for UD Address Vector Table */ 02269 02270 struct hermonprm_udavtable_memory_parameters_st { /* Little Endian */ 02271 pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ 02272 /* -------------- */ 02273 pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ 02274 pseudo_bit_t reserved0[0x00005]; 02275 pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ 02276 pseudo_bit_t reserved1[0x00002]; 02277 /* -------------- */ 02278 }; 02279 02280 /* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */ 02281 02282 struct hermonprm_init_hca_st { /* Little Endian */ 02283 pseudo_bit_t reserved0[0x00018]; 02284 pseudo_bit_t version[0x00008]; 02285 /* -------------- */ 02286 pseudo_bit_t reserved1[0x00040]; 02287 /* -------------- */ 02288 pseudo_bit_t reserved2[0x00010]; 02289 pseudo_bit_t hca_core_clock[0x00010];/* Internal Clock freq in MHz */ 02290 /* -------------- */ 02291 pseudo_bit_t router_qp[0x00018]; /* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet. 02292 Valid only if RE bit is set */ 02293 pseudo_bit_t reserved3[0x00005]; 02294 pseudo_bit_t ipr2[0x00001]; /* Hermon New. IP router on port 2 */ 02295 pseudo_bit_t ipr1[0x00001]; /* Hermon New. IP router on port 1 */ 02296 pseudo_bit_t ibr[0x00001]; /* InfiniBand Router Mode */ 02297 /* -------------- */ 02298 pseudo_bit_t udp[0x00001]; /* UD Port Check Enable 02299 0 - Port field in Address Vector is ignored 02300 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ 02301 pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations 02302 0 - Host is Little Endian 02303 1 - Host is Big endian 02304 */ 02305 pseudo_bit_t reserved4[0x00001]; 02306 pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ 02307 pseudo_bit_t reserved5[0x0001c]; 02308 /* -------------- */ 02309 pseudo_bit_t reserved6[0x00040]; 02310 /* -------------- */ 02311 struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */ 02312 /* -------------- */ 02313 pseudo_bit_t reserved7[0x00100]; 02314 /* -------------- */ 02315 struct hermonprm_multicastparam_st multicast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */ 02316 /* -------------- */ 02317 pseudo_bit_t reserved8[0x00080]; 02318 /* -------------- */ 02319 struct hermonprm_tptparams_st tpt_parameters; 02320 /* -------------- */ 02321 pseudo_bit_t reserved9[0x00080]; 02322 /* -------------- */ 02323 struct hermonprm_uar_params_st uar_parameters;/* UAR Parameters */ 02324 /* -------------- */ 02325 pseudo_bit_t reserved10[0x00600]; 02326 /* -------------- */ 02327 }; 02328 02329 /* Event Queue Context Table Entry #### michal - gdror fixed */ 02330 02331 struct hermonprm_eqc_st { /* Little Endian */ 02332 pseudo_bit_t reserved0[0x00008]; 02333 pseudo_bit_t st[0x00004]; /* Event delivery state machine 02334 0x9 - Armed 02335 0xA - Fired 02336 0xB - Always_Armed (auto-rearm) 02337 other - reserved */ 02338 pseudo_bit_t reserved1[0x00005]; 02339 pseudo_bit_t oi[0x00001]; /* Oerrun ignore. 02340 If set, HW will not check EQ full condition when writing new EQEs. */ 02341 pseudo_bit_t ec[0x00001]; /* is set, all EQEs are written (coalesced) to first EQ entry */ 02342 pseudo_bit_t reserved2[0x00009]; 02343 pseudo_bit_t status[0x00004]; /* EQ status: 02344 0000 - OK 02345 1010 - EQ write failure 02346 Valid for the QUERY_EQ and HW2SW_EQ commands only */ 02347 /* -------------- */ 02348 pseudo_bit_t reserved3[0x00020]; 02349 /* -------------- */ 02350 pseudo_bit_t reserved4[0x00005]; 02351 pseudo_bit_t page_offset[0x00007]; /* offset bits[11:5] of first EQE in the EQ relative to the first page in memory region mapping this EQ */ 02352 pseudo_bit_t reserved5[0x00014]; 02353 /* -------------- */ 02354 pseudo_bit_t reserved6[0x00018]; 02355 pseudo_bit_t log_eq_size[0x00005]; /* Log (base 2) of the EQ size (in entries). Maximum EQ size is 2^22 EQEs (max log_eq_size is 22) */ 02356 pseudo_bit_t reserved7[0x00003]; 02357 /* -------------- */ 02358 pseudo_bit_t eq_max_count[0x00010]; /* Event Generation Moderation counter */ 02359 pseudo_bit_t eq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 02360 /* -------------- */ 02361 pseudo_bit_t intr[0x0000a]; /* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */ 02362 pseudo_bit_t reserved8[0x00016]; 02363 /* -------------- */ 02364 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */ 02365 pseudo_bit_t reserved9[0x00010]; 02366 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 02367 pseudo_bit_t reserved10[0x00002]; 02368 /* -------------- */ 02369 pseudo_bit_t reserved11[0x00003]; 02370 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */ 02371 /* -------------- */ 02372 pseudo_bit_t reserved12[0x00040]; 02373 /* -------------- */ 02374 pseudo_bit_t consumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ. 02375 Must be 0x0 in EQ initialization. 02376 Maintained by HW (valid for the QUERY_EQ command only). */ 02377 pseudo_bit_t reserved13[0x00008]; 02378 /* -------------- */ 02379 pseudo_bit_t producer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ. 02380 EQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a EQE needs to be added. 02381 Maintained by HW (valid for the QUERY_EQ command only) */ 02382 pseudo_bit_t reserved14[0x00008]; 02383 /* -------------- */ 02384 pseudo_bit_t reserved15[0x00080]; 02385 /* -------------- */ 02386 }; 02387 02388 /* Memory Translation Table (MTT) Entry #### michal - match to PRM */ 02389 02390 struct hermonprm_mtt_st { /* Little Endian */ 02391 pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 02392 /* -------------- */ 02393 pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ 02394 pseudo_bit_t reserved0[0x00002]; 02395 pseudo_bit_t ptag_l[0x0001d]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 02396 /* -------------- */ 02397 }; 02398 02399 /* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */ 02400 02401 struct hermonprm_mpt_st { /* Little Endian */ 02402 pseudo_bit_t reserved0[0x00008]; 02403 pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ 02404 pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation is performed for this region */ 02405 pseudo_bit_t lr[0x00001]; /* If set - local read access is enabled. Must be set for all MPT Entries. */ 02406 pseudo_bit_t lw[0x00001]; /* If set - local write access is enabled */ 02407 pseudo_bit_t rr[0x00001]; /* If set - remote read access is enabled. */ 02408 pseudo_bit_t rw[0x00001]; /* If set - remote write access is enabled */ 02409 pseudo_bit_t atomic[0x00001]; /* If set - remote Atomic access is allowed. */ 02410 pseudo_bit_t eb[0x00001]; /* If set - bind is enabled. Valid only for regions. */ 02411 pseudo_bit_t atc_req[0x00001]; /* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */ 02412 pseudo_bit_t atc_xlated[0x00001]; /* If set, uplink cycle to be issues with “ATC_translated” indicator to force bypass of the chipset IOMMU. */ 02413 pseudo_bit_t reserved1[0x00001]; 02414 pseudo_bit_t no_snoop[0x00001]; /* If set, issue PCIe cycle with ûno Snoopÿ attribute - cycle not to be snooped in CPU caches */ 02415 pseudo_bit_t reserved2[0x00008]; 02416 pseudo_bit_t status[0x00004]; /* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */ 02417 /* -------------- */ 02418 pseudo_bit_t reserved3[0x00007]; 02419 pseudo_bit_t bqp[0x00001]; /* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */ 02420 pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ 02421 /* -------------- */ 02422 pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */ 02423 /* -------------- */ 02424 pseudo_bit_t pd[0x00018]; /* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */ 02425 pseudo_bit_t en_rinv[0x00001]; /* Enable remote invalidation */ 02426 pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ 02427 pseudo_bit_t nce[0x00001]; /* Data can be cached in Network Cache (see ûNetwork Cacheÿ on page 81) */ 02428 pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ 02429 pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */ 02430 pseudo_bit_t w_dif[0x00001]; /* Wire space contains dif */ 02431 pseudo_bit_t m_dif[0x00001]; /* Memory space contains dif */ 02432 pseudo_bit_t reserved4[0x00001]; 02433 /* -------------- */ 02434 pseudo_bit_t start_addr_h[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 02435 /* -------------- */ 02436 pseudo_bit_t start_addr_l[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 02437 /* -------------- */ 02438 pseudo_bit_t len_h[0x00020]; /* Region/Window Length */ 02439 /* -------------- */ 02440 pseudo_bit_t len_l[0x00020]; /* Region/Window Length */ 02441 /* -------------- */ 02442 pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ 02443 /* -------------- */ 02444 pseudo_bit_t win_cnt[0x00018]; /* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ 02445 pseudo_bit_t reserved5[0x00008]; 02446 /* -------------- */ 02447 pseudo_bit_t mtt_rep[0x00004]; /* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */ 02448 pseudo_bit_t reserved6[0x00011]; 02449 pseudo_bit_t block_mode[0x00001]; /* If set, the page size is not power of two, and entity_size is in bytes. */ 02450 pseudo_bit_t len64[0x00001]; /* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */ 02451 pseudo_bit_t fbo_en[0x00001]; /* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */ 02452 pseudo_bit_t reserved7[0x00008]; 02453 /* -------------- */ 02454 pseudo_bit_t mtt_adr_h[0x00008]; /* Offset to MTT list for this region. Must be aligned on 8 bytes. */ 02455 pseudo_bit_t reserved8[0x00018]; 02456 /* -------------- */ 02457 pseudo_bit_t mtt_adr_l[0x00020]; /* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */ 02458 /* -------------- */ 02459 pseudo_bit_t mtt_size[0x00020]; /* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */ 02460 /* -------------- */ 02461 pseudo_bit_t entity_size[0x00015]; /* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */ 02462 pseudo_bit_t reserved9[0x0000b]; 02463 /* -------------- */ 02464 pseudo_bit_t mtt_fbo[0x00015]; /* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */ 02465 pseudo_bit_t reserved10[0x0000b]; 02466 /* -------------- */ 02467 }; 02468 02469 /* Completion Queue Context Table Entry #### michal - match PRM */ 02470 02471 struct hermonprm_completion_queue_context_st { /* Little Endian */ 02472 pseudo_bit_t reserved0[0x00008]; 02473 pseudo_bit_t st[0x00004]; /* Event delivery state machine 02474 0x0 - reserved 02475 0x9 - ARMED (Request for Notification) 02476 0x6 - ARMED SOLICITED (Request Solicited Notification) 02477 0xA - FIRED 02478 other - reserved 02479 02480 Must be 0x0 in CQ initialization. 02481 Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 02482 pseudo_bit_t reserved1[0x00005]; 02483 pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. 02484 When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ 02485 pseudo_bit_t cc[0x00001]; /* is set, all CQEs are written (coalesced) to first CQ entry */ 02486 pseudo_bit_t reserved2[0x00009]; 02487 pseudo_bit_t status[0x00004]; /* CQ status 02488 0000 - OK 02489 1001 - CQ overflow 02490 1010 - CQ write failure 02491 Valid for the QUERY_CQ and HW2SW_CQ commands only */ 02492 /* -------------- */ 02493 pseudo_bit_t reserved3[0x00020]; 02494 /* -------------- */ 02495 pseudo_bit_t reserved4[0x00005]; 02496 pseudo_bit_t page_offset[0x00007]; /* offset of first CQE in the CQ relative to the first page in memory region mapping this CQ */ 02497 pseudo_bit_t reserved5[0x00014]; 02498 /* -------------- */ 02499 pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ 02500 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). 02501 Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ 02502 pseudo_bit_t reserved6[0x00003]; 02503 /* -------------- */ 02504 pseudo_bit_t cq_max_count[0x00010]; /* Event Generation Moderation counter */ 02505 pseudo_bit_t cq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 02506 /* -------------- */ 02507 pseudo_bit_t c_eqn[0x00009]; /* Event Queue this CQ reports completion events to. 02508 Valid values are 0 to 63 02509 If configured to value other than 0-63, completion events will not be reported on the CQ. */ 02510 pseudo_bit_t reserved7[0x00017]; 02511 /* -------------- */ 02512 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 02513 pseudo_bit_t reserved8[0x00010]; 02514 pseudo_bit_t log2_page_size[0x00006]; 02515 pseudo_bit_t reserved9[0x00002]; 02516 /* -------------- */ 02517 pseudo_bit_t reserved10[0x00003]; 02518 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 02519 /* -------------- */ 02520 pseudo_bit_t last_notified_indx[0x00018];/* Maintained by HW. 02521 Valid for QUERY_CQ and HW2SW_CQ commands only. */ 02522 pseudo_bit_t reserved11[0x00008]; 02523 /* -------------- */ 02524 pseudo_bit_t solicit_producer_indx[0x00018];/* Maintained by HW. 02525 Valid for QUERY_CQ and HW2SW_CQ commands only. 02526 */ 02527 pseudo_bit_t reserved12[0x00008]; 02528 /* -------------- */ 02529 pseudo_bit_t consumer_counter[0x00018];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. 02530 */ 02531 pseudo_bit_t reserved13[0x00008]; 02532 /* -------------- */ 02533 pseudo_bit_t producer_counter[0x00018];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. 02534 CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. 02535 Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ 02536 pseudo_bit_t reserved14[0x00008]; 02537 /* -------------- */ 02538 pseudo_bit_t reserved15[0x00020]; 02539 /* -------------- */ 02540 pseudo_bit_t reserved16[0x00020]; 02541 /* -------------- */ 02542 pseudo_bit_t db_record_addr_h[0x00020];/* CQ DB Record physical address [63:32] */ 02543 /* -------------- */ 02544 pseudo_bit_t reserved17[0x00003]; 02545 pseudo_bit_t db_record_addr_l[0x0001d];/* CQ DB Record physical address [31:3] */ 02546 /* -------------- */ 02547 }; 02548 02549 /* GPIO_event_data #### michal - gdror fixed */ 02550 02551 struct hermonprm_gpio_event_data_st { /* Little Endian */ 02552 pseudo_bit_t reserved0[0x00060]; 02553 /* -------------- */ 02554 pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 02555 /* -------------- */ 02556 pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 02557 /* -------------- */ 02558 pseudo_bit_t reserved1[0x00020]; 02559 /* -------------- */ 02560 }; 02561 02562 /* Event_data Field - QP/EE Events #### michal - doesn't match PRM */ 02563 02564 struct hermonprm_qp_ee_event_st { /* Little Endian */ 02565 pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for ###michal - field changed to QP number */ 02566 pseudo_bit_t reserved0[0x00008]; 02567 /* -------------- */ 02568 pseudo_bit_t reserved1[0x00020]; 02569 /* -------------- */ 02570 pseudo_bit_t reserved2[0x0001c]; 02571 pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field 02572 Not valid on SRQ events ###michal - field replaced with RESERVED */ 02573 pseudo_bit_t reserved3[0x00003]; 02574 /* -------------- */ 02575 pseudo_bit_t reserved4[0x00060]; 02576 /* -------------- */ 02577 }; 02578 02579 /* InfiniHost-III-EX Type0 Configuration Header ####michal - doesn't match PRM (new fields added, see below) */ 02580 02581 struct hermonprm_mt25208_type0_st { /* Little Endian */ 02582 pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ 02583 pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode 02584 25408 (decimal) - InfiniHost-III EX mode (the mode described in this manual) 02585 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode 02586 */ 02587 /* -------------- */ 02588 pseudo_bit_t command[0x00010]; /* PCI Command Register */ 02589 pseudo_bit_t status[0x00010]; /* PCI Status Register */ 02590 /* -------------- */ 02591 pseudo_bit_t revision_id[0x00008]; 02592 pseudo_bit_t class_code_hca_class_code[0x00018]; 02593 /* -------------- */ 02594 pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ 02595 pseudo_bit_t latency_timer[0x00008]; 02596 pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ 02597 pseudo_bit_t bist[0x00008]; 02598 /* -------------- */ 02599 pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ 02600 pseudo_bit_t reserved0[0x00010]; 02601 pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ 02602 /* -------------- */ 02603 pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ 02604 /* -------------- */ 02605 pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ 02606 pseudo_bit_t reserved1[0x00010]; 02607 pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ 02608 /* -------------- */ 02609 pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ 02610 /* -------------- */ 02611 pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ 02612 pseudo_bit_t reserved2[0x00010]; 02613 pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 02614 /* -------------- */ 02615 pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 02616 /* -------------- */ 02617 pseudo_bit_t cardbus_cis_pointer[0x00020]; 02618 /* -------------- */ 02619 pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ 02620 pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ 02621 /* -------------- */ 02622 pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 02623 pseudo_bit_t reserved3[0x0000a]; 02624 pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 02625 /* -------------- */ 02626 pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ 02627 pseudo_bit_t reserved4[0x00018]; 02628 /* -------------- */ 02629 pseudo_bit_t reserved5[0x00020]; 02630 /* -------------- */ 02631 pseudo_bit_t interrupt_line[0x00008]; 02632 pseudo_bit_t interrupt_pin[0x00008]; 02633 pseudo_bit_t min_gnt[0x00008]; 02634 pseudo_bit_t max_latency[0x00008]; 02635 /* -------------- */ 02636 pseudo_bit_t reserved6[0x00100]; 02637 /* -------------- */ 02638 pseudo_bit_t msi_cap_id[0x00008]; 02639 pseudo_bit_t msi_next_cap_ptr[0x00008]; 02640 pseudo_bit_t msi_en[0x00001]; 02641 pseudo_bit_t multiple_msg_cap[0x00003]; 02642 pseudo_bit_t multiple_msg_en[0x00003]; 02643 pseudo_bit_t cap_64_bit_addr[0x00001]; 02644 pseudo_bit_t reserved7[0x00008]; 02645 /* -------------- */ 02646 pseudo_bit_t msg_addr_l[0x00020]; 02647 /* -------------- */ 02648 pseudo_bit_t msg_addr_h[0x00020]; 02649 /* -------------- */ 02650 pseudo_bit_t msg_data[0x00010]; 02651 pseudo_bit_t reserved8[0x00010]; 02652 /* -------------- */ 02653 pseudo_bit_t reserved9[0x00080]; 02654 /* -------------- */ 02655 pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ 02656 pseudo_bit_t pm_next_cap_ptr[0x00008]; 02657 pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h 02658 [3] PME clock - 0h 02659 [4] RsvP 02660 [5] Device specific initialization - 0h 02661 [8:6] AUX current - 0h 02662 [9] D1 support - 0h 02663 [10] D2 support - 0h 02664 [15:11] PME support - 0h */ 02665 /* -------------- */ 02666 pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ 02667 pseudo_bit_t pm_control_status_brdg_ext[0x00008]; 02668 pseudo_bit_t data[0x00008]; 02669 /* -------------- */ 02670 pseudo_bit_t reserved10[0x00040]; 02671 /* -------------- */ 02672 pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ 02673 pseudo_bit_t vpd_next_cap_id[0x00008]; 02674 pseudo_bit_t vpd_address[0x0000f]; 02675 pseudo_bit_t f[0x00001]; 02676 /* -------------- */ 02677 pseudo_bit_t vpd_data[0x00020]; 02678 /* -------------- */ 02679 pseudo_bit_t reserved11[0x00040]; 02680 /* -------------- */ 02681 pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ 02682 pseudo_bit_t pciex_next_cap_ptr[0x00008]; 02683 pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h 02684 [7:4] Device/Port Type - 0h 02685 [8] Slot implemented - 0h 02686 [13:9] Interrupt message number 02687 */ 02688 /* -------------- */ 02689 pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h 02690 [4:3] Phantom Function supported - 0h 02691 [5] Extended Tag Filed supported - 0h 02692 [8:6] Endpoint L0s Acceptable Latency - TBD 02693 [11:9] Endpoint L1 Acceptable Latency - TBD 02694 [12] Attention Button Present - configured through InfiniBurn 02695 [13] Attention Indicator Present - configured through InfiniBurn 02696 [14] Power Indicator Present - configured through InfiniBurn 02697 [25:18] Captured Slot Power Limit Value 02698 [27:26] Captured Slot Power Limit Scale */ 02699 /* -------------- */ 02700 pseudo_bit_t device_control[0x00010]; 02701 pseudo_bit_t device_status[0x00010]; 02702 /* -------------- */ 02703 pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h 02704 [9:4] Maximum Link Width - 8h 02705 [11:10] Active State Power Management Support - 3h 02706 [14:12] L0s Exit Latency - TBD 02707 [17:15] L1 Exit Latency - TBD 02708 [31:24] Port Number - 0h */ 02709 /* -------------- */ 02710 pseudo_bit_t link_control[0x00010]; 02711 pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h 02712 [9:4] Negotiated Link Width 02713 [12] Slot clock configuration - 1h */ 02714 /* -------------- */ 02715 pseudo_bit_t reserved12[0x00260]; 02716 /* -------------- */ 02717 pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ 02718 pseudo_bit_t capability_version[0x00004];/* 1h */ 02719 pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ 02720 /* -------------- */ 02721 pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status 02722 4 Data Link Protocol Error Status 02723 12 Poisoned TLP Status 02724 13 Flow Control Protocol Error Status 02725 14 Completion Timeout Status 02726 15 Completer Abort Status 02727 16 Unexpected Completion Status 02728 17 Receiver Overflow Status 02729 18 Malformed TLP Status 02730 19 ECRC Error Status 02731 20 Unsupported Request Error Status */ 02732 /* -------------- */ 02733 pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask 02734 4 Data Link Protocol Error Mask 02735 12 Poisoned TLP Mask 02736 13 Flow Control Protocol Error Mask 02737 14 Completion Timeout Mask 02738 15 Completer Abort Mask 02739 16 Unexpected Completion Mask 02740 17 Receiver Overflow Mask 02741 18 Malformed TLP Mask 02742 19 ECRC Error Mask 02743 20 Unsupported Request Error Mask */ 02744 /* -------------- */ 02745 pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity 02746 4 Data Link Protocol Error Severity 02747 12 Poisoned TLP Severity 02748 13 Flow Control Protocol Error Severity 02749 14 Completion Timeout Severity 02750 15 Completer Abort Severity 02751 16 Unexpected Completion Severity 02752 17 Receiver Overflow Severity 02753 18 Malformed TLP Severity 02754 19 ECRC Error Severity 02755 20 Unsupported Request Error Severity */ 02756 /* -------------- */ 02757 pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status 02758 6 Bad TLP Status 02759 7 Bad DLLP Status 02760 8 REPLAY_NUM Rollover Status 02761 12 Replay Timer Timeout Status */ 02762 /* -------------- */ 02763 pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask 02764 6 Bad TLP Mask 02765 7 Bad DLLP Mask 02766 8 REPLAY_NUM Rollover Mask 02767 12 Replay Timer Timeout Mask */ 02768 /* -------------- */ 02769 pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; 02770 /* -------------- */ 02771 struct hermonprm_header_log_register_st header_log_register; 02772 /* -------------- */ 02773 pseudo_bit_t reserved13[0x006a0]; 02774 /* -------------- */ 02775 }; 02776 02777 /* Event Data Field - Performance Monitor */ 02778 02779 struct hermonprm_performance_monitor_event_st { /* Little Endian */ 02780 struct hermonprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ 02781 /* -------------- */ 02782 pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC 02783 0x02 - RQPC 02784 0x03 - CQC 02785 0x04 - Rkey 02786 0x05 - TLB 02787 0x06 - port0 02788 0x07 - port1 */ 02789 pseudo_bit_t reserved0[0x00018]; 02790 /* -------------- */ 02791 pseudo_bit_t reserved1[0x00040]; 02792 /* -------------- */ 02793 }; 02794 02795 /* Event_data Field - Page Faults */ 02796 02797 struct hermonprm_page_fault_event_data_st { /* Little Endian */ 02798 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 02799 /* -------------- */ 02800 pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 02801 /* -------------- */ 02802 pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ 02803 /* -------------- */ 02804 pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ 02805 pseudo_bit_t reserved0[0x00003]; 02806 pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ 02807 pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ 02808 pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ 02809 pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ 02810 pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ 02811 /* -------------- */ 02812 pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ 02813 pseudo_bit_t reserved1[0x00008]; 02814 /* -------------- */ 02815 pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ 02816 /* -------------- */ 02817 }; 02818 02819 /* WQE segments format */ 02820 02821 struct hermonprm_wqe_segment_st { /* Little Endian */ 02822 struct hermonprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ 02823 /* -------------- */ 02824 pseudo_bit_t reserved0[0x00280]; 02825 /* -------------- */ 02826 struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ 02827 /* -------------- */ 02828 pseudo_bit_t reserved1[0x00100]; 02829 /* -------------- */ 02830 pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */ 02831 /* -------------- */ 02832 pseudo_bit_t reserved2[0x00080]; 02833 /* -------------- */ 02834 }; 02835 02836 /* Event_data Field - Port State Change #### michal - match PRM */ 02837 02838 struct hermonprm_port_state_change_st { /* Little Endian */ 02839 pseudo_bit_t reserved0[0x00040]; 02840 /* -------------- */ 02841 pseudo_bit_t reserved1[0x0001c]; 02842 pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ 02843 pseudo_bit_t reserved2[0x00002]; 02844 /* -------------- */ 02845 pseudo_bit_t reserved3[0x00060]; 02846 /* -------------- */ 02847 }; 02848 02849 /* Event_data Field - Completion Queue Error #### michal - match PRM */ 02850 02851 struct hermonprm_completion_queue_error_st { /* Little Endian */ 02852 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 02853 pseudo_bit_t reserved0[0x00008]; 02854 /* -------------- */ 02855 pseudo_bit_t reserved1[0x00020]; 02856 /* -------------- */ 02857 pseudo_bit_t syndrome[0x00008]; /* Error syndrome 02858 0x01 - CQ overrun 02859 0x02 - CQ access violation error */ 02860 pseudo_bit_t reserved2[0x00018]; 02861 /* -------------- */ 02862 pseudo_bit_t reserved3[0x00060]; 02863 /* -------------- */ 02864 }; 02865 02866 /* Event_data Field - Completion Event #### michal - match PRM */ 02867 02868 struct hermonprm_completion_event_st { /* Little Endian */ 02869 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 02870 pseudo_bit_t reserved0[0x00008]; 02871 /* -------------- */ 02872 pseudo_bit_t reserved1[0x000a0]; 02873 /* -------------- */ 02874 }; 02875 02876 /* Event Queue Entry #### michal - match to PRM */ 02877 02878 struct hermonprm_event_queue_entry_st { /* Little Endian */ 02879 pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. 02880 Defined for events which have sub types, zero elsewhere. */ 02881 pseudo_bit_t reserved0[0x00008]; 02882 pseudo_bit_t event_type[0x00008]; /* Event Type */ 02883 pseudo_bit_t reserved1[0x00008]; 02884 /* -------------- */ 02885 pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ 02886 /* -------------- */ 02887 pseudo_bit_t reserved2[0x00007]; 02888 pseudo_bit_t owner[0x00001]; /* Owner of the entry 02889 0 SW 02890 1 HW */ 02891 pseudo_bit_t reserved3[0x00018]; 02892 /* -------------- */ 02893 }; 02894 02895 /* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */ 02896 02897 struct hermonprm_qp_ee_state_transitions_st { /* Little Endian */ 02898 pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ 02899 /* -------------- */ 02900 pseudo_bit_t reserved0[0x00020]; 02901 /* -------------- */ 02902 struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */ 02903 /* -------------- */ 02904 pseudo_bit_t reserved1[0x00800]; 02905 /* -------------- */ 02906 }; 02907 02908 /* Completion Queue Entry Format #### michal - fixed by gdror */ 02909 02910 struct hermonprm_completion_queue_entry_st { /* Little Endian */ 02911 pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 02912 pseudo_bit_t reserved0[0x00002]; 02913 pseudo_bit_t d2s[0x00001]; /* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers 02914 packet only to send-associated sniffer receive queue. */ 02915 pseudo_bit_t fcrc_sd[0x00001]; /* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only. 02916 SD: CQ associated with Sniffer receive queue. If set, packets were skipped due to lack of receive buffers on the Sniffer receive queue */ 02917 pseudo_bit_t fl[0x00001]; /* Force Loopback Valid for responder RawEth and UD only. */ 02918 pseudo_bit_t vlan[0x00002]; /* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue 02919 00 - No VLAN header was present in the packet 02920 01 - C-VLAN (802.1q) Header was present in the frame. 02921 10 - S-VLAN (802.1ad) Header was present in the frame. */ 02922 pseudo_bit_t dife[0x00001]; /* DIF Error */ 02923 /* -------------- */ 02924 pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message. 02925 For a responder CQE, if completed WQE Opcode is Send With Invalidate, this field contains the R_key that was invalidated. 02926 For a responder CQE of a GSI packet this filed contains the Pkey Index of the packet. 02927 For IPoIB (UD) and RawEth CQEs this field contains the RSS hash function value. 02928 Otherwise, this field is reserved. */ 02929 /* -------------- */ 02930 pseudo_bit_t srq_rqpn[0x00018]; /* For Responder UD QPs, Remote (source) QP number. 02931 For Responder SRC QPs, SRQ number. 02932 Otherwise, this field is reserved. */ 02933 pseudo_bit_t ml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast. 02934 For responder UD over Ethernet and RawEth CQEs: Index of the MAC Table entry that the packet DMAC was matched against. 02935 Otherwise, this field is reserved. */ 02936 pseudo_bit_t g[0x00001]; /* For responder UD over IB CQE this bit indicates the presence of a GRH 02937 For responder UD over Ethernet CQE this bit is set if IPv6 L3 header was present in the packet, this bit is cleared if IPv4 L3 Header was present in the packet. 02938 Otherwise, this field is reserved. */ 02939 /* -------------- */ 02940 pseudo_bit_t slid_smac47_32[0x00010];/* For responder UD over IB CQE it is the source LID of the packet. 02941 For responder UD over Ethernet and RawEth CQEs it is the source-MAC[47:32] of the packet. 02942 Otherwise, this field is reserved. */ 02943 pseudo_bit_t vid[0x0000c]; /* Frame VID, valid for Responder Raw Ethernet and UD over Ethernet QP. Otherwise, this field is reserved. */ 02944 pseudo_bit_t sl[0x00004]; /* For responder UD over IB - the Service Level of the packet. 02945 For responder UD over Ethernet and RawEth - it is VLAN-header[15:12] 02946 Otherwise, this field is reserved. */ 02947 /* -------------- */ 02948 pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020];/* For responder UD over Ethernet - source MAC[31:0] of the packet. 02949 For responder RawEth and UD over IB - RawEth-IPoIB status {3 reserved, ipok,udp,tcp,ipv4opt,ipv6,ipv4vf,ipv4,rht(6),ipv6extmask(6),reserved(2),l2am,reserved(2),bfcs,reserved(2),enc} 02950 Otherwise, this field is reserved. */ 02951 /* -------------- */ 02952 pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data transferred. Applicable for RDMA-read, Atomic and all receive operations. completions. 02953 For Receive Queue that is subject for headers. separation, byte_cnt[31:24] specify number of bytes scattered to the first scatter entry (headers. length). Byte_cnt[23:0] specify total byte count received (including headers). */ 02954 /* -------------- */ 02955 pseudo_bit_t checksum[0x00010]; /* Valid for RawEth and IPoIB only. */ 02956 pseudo_bit_t wqe_counter[0x00010]; 02957 /* -------------- */ 02958 pseudo_bit_t opcode[0x00005]; /* Send completions - same encoding as WQE. 02959 Error coding is 0x1F 02960 Receive: 02961 0x0 - RDMA-Write with Immediate 02962 0x1 - Send 02963 0x2 - Send with Immediate 02964 0x3 - Send & Invalidate 02965 */ 02966 pseudo_bit_t is[0x00001]; /* inline scatter */ 02967 pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 02968 pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 02969 pseudo_bit_t reserved1[0x00010]; 02970 pseudo_bit_t reserved2[0x00008]; 02971 /* -------------- */ 02972 }; 02973 02974 /* */ 02975 02976 struct hermonprm_mcg_qps_st { /* Little Endian */ 02977 struct hermonprm_mcg_qp_dw_st dw[128]; 02978 /* -------------- */ 02979 }; 02980 02981 /* */ 02982 02983 struct hermonprm_mcg_hdr_st { /* Little Endian */ 02984 pseudo_bit_t reserved0[0x00006]; 02985 pseudo_bit_t next_mcg[0x0001a]; 02986 /* -------------- */ 02987 pseudo_bit_t members_count[0x00018]; 02988 pseudo_bit_t reserved1[0x00008]; 02989 /* -------------- */ 02990 pseudo_bit_t reserved2[0x00020]; 02991 /* -------------- */ 02992 pseudo_bit_t reserved3[0x00020]; 02993 /* -------------- */ 02994 pseudo_bit_t gid3[0x00020]; 02995 /* -------------- */ 02996 pseudo_bit_t gid2[0x00020]; 02997 /* -------------- */ 02998 pseudo_bit_t gid1[0x00020]; 02999 /* -------------- */ 03000 pseudo_bit_t gid0[0x00020]; 03001 /* -------------- */ 03002 }; 03003 03004 /* */ 03005 03006 struct hermonprm_sched_queue_context_st { /* Little Endian */ 03007 pseudo_bit_t policy[0x00003]; /* Schedule Queue Policy - 0 - LLSQ, 1 - GBSQ, 2 - BESQ */ 03008 pseudo_bit_t vl15[0x00001]; 03009 pseudo_bit_t sl[0x00004]; /* SL this Schedule Queue is associated with (if vl15 bit is 0) */ 03010 pseudo_bit_t port[0x00002]; /* Port this Schedule Queue is associated with */ 03011 pseudo_bit_t reserved0[0x00006]; 03012 pseudo_bit_t weight[0x00010]; /* Weight of this SchQ */ 03013 /* -------------- */ 03014 }; 03015 03016 /* */ 03017 03018 struct hermonprm_ecc_detect_event_data_st { /* Little Endian */ 03019 pseudo_bit_t reserved0[0x00080]; 03020 /* -------------- */ 03021 pseudo_bit_t cause_lsb[0x00001]; 03022 pseudo_bit_t reserved1[0x00002]; 03023 pseudo_bit_t cause_msb[0x00001]; 03024 pseudo_bit_t reserved2[0x00002]; 03025 pseudo_bit_t err_rmw[0x00001]; 03026 pseudo_bit_t err_src_id[0x00003]; 03027 pseudo_bit_t err_da[0x00002]; 03028 pseudo_bit_t err_ba[0x00002]; 03029 pseudo_bit_t reserved3[0x00011]; 03030 pseudo_bit_t overflow[0x00001]; 03031 /* -------------- */ 03032 pseudo_bit_t err_ra[0x00010]; 03033 pseudo_bit_t err_ca[0x00010]; 03034 /* -------------- */ 03035 }; 03036 03037 /* Event_data Field - ECC Detection Event */ 03038 03039 struct hermonprm_scrubbing_event_st { /* Little Endian */ 03040 pseudo_bit_t reserved0[0x00080]; 03041 /* -------------- */ 03042 pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: 03043 single ECC error in the 64bit lsb data, on the rise edge of the clock */ 03044 pseudo_bit_t reserved1[0x00002]; 03045 pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: 03046 single ECC error in the 64bit msb data, on the fall edge of the clock */ 03047 pseudo_bit_t reserved2[0x00002]; 03048 pseudo_bit_t err_rmw[0x00001]; /* transaction type: 03049 0 - read 03050 1 - read/modify/write */ 03051 pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ 03052 pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ 03053 pseudo_bit_t err_ba[0x00002]; /* Error bank address */ 03054 pseudo_bit_t reserved3[0x00011]; 03055 pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ 03056 /* -------------- */ 03057 pseudo_bit_t err_ra[0x00010]; /* Error row address */ 03058 pseudo_bit_t err_ca[0x00010]; /* Error column address */ 03059 /* -------------- */ 03060 }; 03061 03062 /* */ 03063 03064 struct hermonprm_eq_cmd_doorbell_st { /* Little Endian */ 03065 pseudo_bit_t reserved0[0x00020]; 03066 /* -------------- */ 03067 }; 03068 03069 /* 0 */ 03070 03071 struct hermonprm_hermon_prm_st { /* Little Endian */ 03072 struct hermonprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ 03073 /* -------------- */ 03074 pseudo_bit_t reserved0[0x7ff00]; 03075 /* -------------- */ 03076 struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ 03077 /* -------------- */ 03078 pseudo_bit_t reserved1[0x7f000]; 03079 /* -------------- */ 03080 struct hermonprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ 03081 /* -------------- */ 03082 pseudo_bit_t reserved2[0x7ff00]; 03083 /* -------------- */ 03084 struct hermonprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ 03085 /* -------------- */ 03086 pseudo_bit_t reserved3[0x7ff40]; 03087 /* -------------- */ 03088 struct hermonprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ 03089 /* -------------- */ 03090 pseudo_bit_t reserved4[0x7ff40]; 03091 /* -------------- */ 03092 struct hermonprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ 03093 /* -------------- */ 03094 pseudo_bit_t reserved5[0x7ff40]; 03095 /* -------------- */ 03096 struct hermonprm_wqe_segment_st wqe_segment;/* WQE segments format */ 03097 /* -------------- */ 03098 pseudo_bit_t reserved6[0x7f000]; 03099 /* -------------- */ 03100 struct hermonprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ 03101 /* -------------- */ 03102 pseudo_bit_t reserved7[0x7ff40]; 03103 /* -------------- */ 03104 struct hermonprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ 03105 /* -------------- */ 03106 pseudo_bit_t reserved8[0xfff20]; 03107 /* -------------- */ 03108 struct hermonprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ 03109 /* -------------- */ 03110 pseudo_bit_t reserved9[0x7f000]; 03111 /* -------------- */ 03112 struct hermonprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ 03113 /* -------------- */ 03114 pseudo_bit_t reserved10[0x00040]; 03115 /* -------------- */ 03116 struct hermonprm_gpio_event_data_st gpio_event_data; 03117 /* -------------- */ 03118 pseudo_bit_t reserved11[0x7fe40]; 03119 /* -------------- */ 03120 struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 03121 /* -------------- */ 03122 pseudo_bit_t reserved12[0x7ff00]; 03123 /* -------------- */ 03124 struct hermonprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ 03125 /* -------------- */ 03126 pseudo_bit_t reserved13[0x7f840]; 03127 /* -------------- */ 03128 struct hermonprm_address_path_st address_path;/* Address Path */ 03129 /* -------------- */ 03130 pseudo_bit_t reserved14[0x7fea0]; 03131 /* -------------- */ 03132 struct hermonprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ 03133 /* -------------- */ 03134 pseudo_bit_t reserved15[0x7fe00]; 03135 /* -------------- */ 03136 struct hermonprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ 03137 /* -------------- */ 03138 pseudo_bit_t reserved16[0x7fe00]; 03139 /* -------------- */ 03140 struct hermonprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ 03141 /* -------------- */ 03142 pseudo_bit_t reserved17[0x7ffc0]; 03143 /* -------------- */ 03144 struct hermonprm_eqc_st eqc; /* Event Queue Context Table Entry */ 03145 /* -------------- */ 03146 pseudo_bit_t reserved18[0x7fe00]; 03147 /* -------------- */ 03148 struct hermonprm_performance_monitors_st performance_monitors;/* Performance Monitors */ 03149 /* -------------- */ 03150 pseudo_bit_t reserved19[0x7ff80]; 03151 /* -------------- */ 03152 struct hermonprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ 03153 /* -------------- */ 03154 pseudo_bit_t reserved20[0xfff20]; 03155 /* -------------- */ 03156 struct hermonprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ 03157 /* -------------- */ 03158 pseudo_bit_t reserved21[0x7f000]; 03159 /* -------------- */ 03160 struct hermonprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ 03161 /* -------------- */ 03162 pseudo_bit_t reserved22[0x7fc00]; 03163 /* -------------- */ 03164 struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ 03165 /* -------------- */ 03166 pseudo_bit_t reserved23[0x7ffc0]; 03167 /* -------------- */ 03168 struct hermonprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ 03169 /* -------------- */ 03170 pseudo_bit_t reserved24[0x7ff00]; 03171 /* -------------- */ 03172 struct hermonprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ 03173 /* -------------- */ 03174 pseudo_bit_t reserved25[0x7ff00]; 03175 /* -------------- */ 03176 pseudo_bit_t reserved26[0x00800]; 03177 /* -------------- */ 03178 pseudo_bit_t reserved27[0x00100]; 03179 /* -------------- */ 03180 pseudo_bit_t reserved28[0x7f700]; 03181 /* -------------- */ 03182 pseudo_bit_t reserved29[0x00100]; 03183 /* -------------- */ 03184 pseudo_bit_t reserved30[0x7ff00]; 03185 /* -------------- */ 03186 struct hermonprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ 03187 /* -------------- */ 03188 pseudo_bit_t reserved31[0x7f800]; 03189 /* -------------- */ 03190 struct hermonprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ 03191 /* -------------- */ 03192 pseudo_bit_t reserved32[0x7f800]; 03193 /* -------------- */ 03194 struct hermonprm_query_dev_cap_st query_dev_cap;/* Query Device Limitations */ 03195 /* -------------- */ 03196 pseudo_bit_t reserved33[0x7f800]; 03197 /* -------------- */ 03198 struct hermonprm_uar_params_st uar_params;/* UAR Parameters */ 03199 /* -------------- */ 03200 pseudo_bit_t reserved34[0x7ff00]; 03201 /* -------------- */ 03202 struct hermonprm_init_port_st init_port;/* INIT_PORT Parameters */ 03203 /* -------------- */ 03204 pseudo_bit_t reserved35[0x7f800]; 03205 /* -------------- */ 03206 struct hermonprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ 03207 /* -------------- */ 03208 pseudo_bit_t reserved36[0x7fe00]; 03209 /* -------------- */ 03210 struct hermonprm_set_ib_st set_ib; /* SET_IB Parameters */ 03211 /* -------------- */ 03212 pseudo_bit_t reserved37[0x7fe00]; 03213 /* -------------- */ 03214 struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ 03215 /* -------------- */ 03216 pseudo_bit_t reserved38[0x7ff80]; 03217 /* -------------- */ 03218 struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 03219 /* -------------- */ 03220 pseudo_bit_t reserved39[0x7ffc0]; 03221 /* -------------- */ 03222 struct hermonprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ 03223 /* -------------- */ 03224 pseudo_bit_t reserved40[0x7ffc0]; 03225 /* -------------- */ 03226 struct hermonprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ 03227 /* -------------- */ 03228 pseudo_bit_t reserved41[0xfffc0]; 03229 /* -------------- */ 03230 struct hermonprm_uar_st uar; /* User Access Region */ 03231 /* -------------- */ 03232 pseudo_bit_t reserved42[0x7c000]; 03233 /* -------------- */ 03234 struct hermonprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ 03235 /* -------------- */ 03236 pseudo_bit_t reserved43[0x7ffe0]; 03237 /* -------------- */ 03238 struct hermonprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ 03239 /* -------------- */ 03240 pseudo_bit_t reserved44[0x7f800]; 03241 /* -------------- */ 03242 struct hermonprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ 03243 /* -------------- */ 03244 pseudo_bit_t reserved45[0x00900]; 03245 /* -------------- */ 03246 struct hermonprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ 03247 /* -------------- */ 03248 pseudo_bit_t reserved46[0x7e6e0]; 03249 /* -------------- */ 03250 struct hermonprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ 03251 /* -------------- */ 03252 pseudo_bit_t reserved47[0x7fe00]; 03253 /* -------------- */ 03254 struct hermonprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ 03255 /* -------------- */ 03256 pseudo_bit_t reserved48[0x7ff00]; 03257 /* -------------- */ 03258 struct hermonprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ 03259 /* -------------- */ 03260 pseudo_bit_t reserved49[0x7ff40]; 03261 /* -------------- */ 03262 struct hermonprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ 03263 /* -------------- */ 03264 pseudo_bit_t reserved50[0x7f000]; 03265 /* -------------- */ 03266 struct hermonprm_performance_counters_st performance_counters;/* Performance Counters */ 03267 /* -------------- */ 03268 pseudo_bit_t reserved51[0x9ff800]; 03269 /* -------------- */ 03270 struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 03271 /* -------------- */ 03272 pseudo_bit_t reserved52[0x7ff00]; 03273 /* -------------- */ 03274 struct hermonprm_pbl_st pbl; /* Physical Buffer List */ 03275 /* -------------- */ 03276 pseudo_bit_t reserved53[0x7ff00]; 03277 /* -------------- */ 03278 struct hermonprm_srq_context_st srq_context;/* SRQ Context */ 03279 /* -------------- */ 03280 pseudo_bit_t reserved54[0x7fe80]; 03281 /* -------------- */ 03282 struct hermonprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ 03283 /* -------------- */ 03284 pseudo_bit_t reserved55[0x7f800]; 03285 /* -------------- */ 03286 struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ 03287 /* -------------- */ 03288 pseudo_bit_t reserved56[0x7ff80]; 03289 /* -------------- */ 03290 struct hermonprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ 03291 /* -------------- */ 03292 pseudo_bit_t reserved57[0x7ffc0]; 03293 /* -------------- */ 03294 struct hermonprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ 03295 /* -------------- */ 03296 pseudo_bit_t reserved58[0x7ffc0]; 03297 /* -------------- */ 03298 struct hermonprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ 03299 /* -------------- */ 03300 pseudo_bit_t reserved59[0x00020]; 03301 /* -------------- */ 03302 pseudo_bit_t reserved60[0x1fffc0]; 03303 /* -------------- */ 03304 struct hermonprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ 03305 /* -------------- */ 03306 struct hermonprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ 03307 /* -------------- */ 03308 pseudo_bit_t reserved61[0x01000]; 03309 /* -------------- */ 03310 pseudo_bit_t reserved62[0x00040]; 03311 /* -------------- */ 03312 pseudo_bit_t reserved63[0x00fc0]; 03313 /* -------------- */ 03314 struct hermonprm_clr_int_st clr_int; /* Clear Interrupt Register */ 03315 /* -------------- */ 03316 pseudo_bit_t reserved64[0xffcfc0]; 03317 /* -------------- */ 03318 }; 03319 #endif /* H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H */
1.5.7.1