00001 /* 00002 This software is available to you under a choice of one of two 00003 licenses. You may choose to be licensed under the terms of the GNU 00004 General Public License (GPL) Version 2, available at 00005 <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD 00006 license, available in the LICENSE.TXT file accompanying this 00007 software. These details are also available at 00008 <http://openib.org/license.html>. 00009 00010 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 00011 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00012 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 00013 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 00014 BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 00015 ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 00016 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 00017 SOFTWARE. 00018 00019 Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. 00020 */ 00021 00022 FILE_LICENCE ( GPL2_ONLY ); 00023 00024 /*** 00025 *** This file was generated at "Tue Nov 22 15:21:23 2005" 00026 *** by: 00027 *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix arbelprm_ -bits -fixnames MT25218_PRM.csp 00028 ***/ 00029 00030 #ifndef H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H 00031 #define H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H 00032 00033 /* UD Address Vector */ 00034 00035 struct arbelprm_ud_address_vector_st { /* Little Endian */ 00036 pseudo_bit_t pd[0x00018]; /* Protection Domain */ 00037 pseudo_bit_t port_number[0x00002]; /* Port number 00038 1 - Port 1 00039 2 - Port 2 00040 other - reserved */ 00041 pseudo_bit_t reserved0[0x00006]; 00042 /* -------------- */ 00043 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 00044 pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 00045 pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 00046 pseudo_bit_t reserved1[0x00008]; 00047 /* -------------- */ 00048 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 00049 pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. 00050 0 - 4X injection rate 00051 1 - 1X injection rate 00052 other - reserved 00053 */ 00054 pseudo_bit_t reserved2[0x00001]; 00055 pseudo_bit_t msg[0x00002]; /* Max Message size, size is 256*2^MSG bytes */ 00056 pseudo_bit_t reserved3[0x00002]; 00057 pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table 00058 mgid_index = (port_number-1) * 2^log_max_gid + gid_index 00059 Where: 00060 1. log_max_gid is taken from QUERY_DEV_LIM command 00061 2. gid_index is the index to the GID table */ 00062 pseudo_bit_t reserved4[0x0000a]; 00063 /* -------------- */ 00064 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 00065 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 00066 pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 00067 /* -------------- */ 00068 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 00069 /* -------------- */ 00070 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 00071 /* -------------- */ 00072 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 00073 /* -------------- */ 00074 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ 00075 /* -------------- */ 00076 }; 00077 00078 /* Send doorbell */ 00079 00080 struct arbelprm_send_doorbell_st { /* Little Endian */ 00081 pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ 00082 pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ 00083 pseudo_bit_t reserved0[0x00002]; 00084 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ 00085 pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ 00086 /* -------------- */ 00087 pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ 00088 pseudo_bit_t reserved1[0x00002]; 00089 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 00090 /* -------------- */ 00091 }; 00092 00093 /* ACCESS_LAM_inject_errors_input_modifier */ 00094 00095 struct arbelprm_access_lam_inject_errors_input_modifier_st { /* Little Endian */ 00096 pseudo_bit_t index3[0x00007]; 00097 pseudo_bit_t q3[0x00001]; 00098 pseudo_bit_t index2[0x00007]; 00099 pseudo_bit_t q2[0x00001]; 00100 pseudo_bit_t index1[0x00007]; 00101 pseudo_bit_t q1[0x00001]; 00102 pseudo_bit_t index0[0x00007]; 00103 pseudo_bit_t q0[0x00001]; 00104 /* -------------- */ 00105 }; 00106 00107 /* ACCESS_LAM_inject_errors_input_parameter */ 00108 00109 struct arbelprm_access_lam_inject_errors_input_parameter_st { /* Little Endian */ 00110 pseudo_bit_t ba[0x00002]; /* Bank Address */ 00111 pseudo_bit_t da[0x00002]; /* Dimm Address */ 00112 pseudo_bit_t reserved0[0x0001c]; 00113 /* -------------- */ 00114 pseudo_bit_t ra[0x00010]; /* Row Address */ 00115 pseudo_bit_t ca[0x00010]; /* Column Address */ 00116 /* -------------- */ 00117 }; 00118 00119 /* */ 00120 00121 struct arbelprm_recv_wqe_segment_next_st { /* Little Endian */ 00122 pseudo_bit_t reserved0[0x00006]; 00123 pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */ 00124 /* -------------- */ 00125 pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes). 00126 Zero value in NDS field signals end of WQEs? chain. 00127 */ 00128 pseudo_bit_t reserved1[0x0001a]; 00129 /* -------------- */ 00130 }; 00131 00132 /* Send wqe segment data inline */ 00133 00134 struct arbelprm_wqe_segment_data_inline_st { /* Little Endian */ 00135 pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ 00136 pseudo_bit_t reserved0[0x00015]; 00137 pseudo_bit_t always1[0x00001]; 00138 /* -------------- */ 00139 pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ 00140 pseudo_bit_t reserved1[0x00008]; 00141 /* -------------- */ 00142 pseudo_bit_t reserved2[0x00040]; 00143 /* -------------- */ 00144 }; 00145 00146 /* Send wqe segment data ptr */ 00147 00148 struct arbelprm_wqe_segment_data_ptr_st { /* Little Endian */ 00149 pseudo_bit_t byte_count[0x0001f]; 00150 pseudo_bit_t always0[0x00001]; 00151 /* -------------- */ 00152 pseudo_bit_t l_key[0x00020]; 00153 /* -------------- */ 00154 pseudo_bit_t local_address_h[0x00020]; 00155 /* -------------- */ 00156 pseudo_bit_t local_address_l[0x00020]; 00157 /* -------------- */ 00158 }; 00159 00160 /* Send wqe segment rd */ 00161 00162 struct arbelprm_local_invalidate_segment_st { /* Little Endian */ 00163 pseudo_bit_t reserved0[0x00040]; 00164 /* -------------- */ 00165 pseudo_bit_t mem_key[0x00018]; 00166 pseudo_bit_t reserved1[0x00008]; 00167 /* -------------- */ 00168 pseudo_bit_t reserved2[0x000a0]; 00169 /* -------------- */ 00170 }; 00171 00172 /* Fast_Registration_Segment */ 00173 00174 struct arbelprm_fast_registration_segment_st { /* Little Endian */ 00175 pseudo_bit_t reserved0[0x0001b]; 00176 pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ 00177 pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ 00178 pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ 00179 pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ 00180 pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ 00181 /* -------------- */ 00182 pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list */ 00183 /* -------------- */ 00184 pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. */ 00185 /* -------------- */ 00186 pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 00187 page_size should be less than 20. */ 00188 pseudo_bit_t reserved1[0x00002]; 00189 pseudo_bit_t zb[0x00001]; /* Zero Based Region */ 00190 pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list */ 00191 /* -------------- */ 00192 pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ 00193 /* -------------- */ 00194 pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ 00195 /* -------------- */ 00196 pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ 00197 /* -------------- */ 00198 pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ 00199 /* -------------- */ 00200 }; 00201 00202 /* Send wqe segment atomic */ 00203 00204 struct arbelprm_wqe_segment_atomic_st { /* Little Endian */ 00205 pseudo_bit_t swap_add_h[0x00020]; 00206 /* -------------- */ 00207 pseudo_bit_t swap_add_l[0x00020]; 00208 /* -------------- */ 00209 pseudo_bit_t compare_h[0x00020]; 00210 /* -------------- */ 00211 pseudo_bit_t compare_l[0x00020]; 00212 /* -------------- */ 00213 }; 00214 00215 /* Send wqe segment remote address */ 00216 00217 struct arbelprm_wqe_segment_remote_address_st { /* Little Endian */ 00218 pseudo_bit_t remote_virt_addr_h[0x00020]; 00219 /* -------------- */ 00220 pseudo_bit_t remote_virt_addr_l[0x00020]; 00221 /* -------------- */ 00222 pseudo_bit_t rkey[0x00020]; 00223 /* -------------- */ 00224 pseudo_bit_t reserved0[0x00020]; 00225 /* -------------- */ 00226 }; 00227 00228 /* end wqe segment bind */ 00229 00230 struct arbelprm_wqe_segment_bind_st { /* Little Endian */ 00231 pseudo_bit_t reserved0[0x0001d]; 00232 pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ 00233 pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. 00234 */ 00235 pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ 00236 /* -------------- */ 00237 pseudo_bit_t reserved1[0x0001e]; 00238 pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ 00239 pseudo_bit_t type[0x00001]; /* Window type. 00240 0 - Type one window 00241 1 - Type two window 00242 */ 00243 /* -------------- */ 00244 pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ 00245 /* -------------- */ 00246 pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ 00247 /* -------------- */ 00248 pseudo_bit_t start_address_h[0x00020]; 00249 /* -------------- */ 00250 pseudo_bit_t start_address_l[0x00020]; 00251 /* -------------- */ 00252 pseudo_bit_t length_h[0x00020]; 00253 /* -------------- */ 00254 pseudo_bit_t length_l[0x00020]; 00255 /* -------------- */ 00256 }; 00257 00258 /* Send wqe segment ud */ 00259 00260 struct arbelprm_wqe_segment_ud_st { /* Little Endian */ 00261 struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 00262 /* -------------- */ 00263 pseudo_bit_t destination_qp[0x00018]; 00264 pseudo_bit_t reserved0[0x00008]; 00265 /* -------------- */ 00266 pseudo_bit_t q_key[0x00020]; 00267 /* -------------- */ 00268 pseudo_bit_t reserved1[0x00040]; 00269 /* -------------- */ 00270 }; 00271 00272 /* Send wqe segment rd */ 00273 00274 struct arbelprm_wqe_segment_rd_st { /* Little Endian */ 00275 pseudo_bit_t destination_qp[0x00018]; 00276 pseudo_bit_t reserved0[0x00008]; 00277 /* -------------- */ 00278 pseudo_bit_t q_key[0x00020]; 00279 /* -------------- */ 00280 pseudo_bit_t reserved1[0x00040]; 00281 /* -------------- */ 00282 }; 00283 00284 /* Send wqe segment ctrl */ 00285 00286 struct arbelprm_wqe_segment_ctrl_send_st { /* Little Endian */ 00287 pseudo_bit_t always1[0x00001]; 00288 pseudo_bit_t s[0x00001]; /* Solicited Event bit. If set, SE (Solicited Event) bit is set in the (last packet of) message. */ 00289 pseudo_bit_t e[0x00001]; /* Event bit. If set, event is generated upon WQE?s completion, if QP is allowed to generate an event. Every WQE with E-bit set generates an event. The C bit must be set on unsignalled QPs if the E bit is set. */ 00290 pseudo_bit_t c[0x00001]; /* Completion Queue bit. Valid for unsignalled QPs only. If set, the CQ is updated upon WQE?s completion */ 00291 pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ 00292 pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ 00293 pseudo_bit_t reserved0[0x00001]; 00294 pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ 00295 pseudo_bit_t reserved1[0x00018]; 00296 /* -------------- */ 00297 pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ 00298 /* -------------- */ 00299 }; 00300 00301 /* Send wqe segment next */ 00302 00303 struct arbelprm_wqe_segment_next_st { /* Little Endian */ 00304 pseudo_bit_t nopcode[0x00005]; /* Next Opcode: OpCode to be used in the next WQE. Encodes the type of operation to be executed on the QP: 00305 ?00000? - NOP. WQE with this opcode creates a completion, but does nothing else 00306 ?01000? - RDMA-write 00307 ?01001? - RDMA-Write with Immediate 00308 ?10000? - RDMA-read 00309 ?10001? - Atomic Compare & swap 00310 ?10010? - Atomic Fetch & Add 00311 ?11000? - Bind memory window 00312 00313 The encoding for the following operations depends on the QP type: 00314 For RC, UC and RD QP: 00315 ?01010? - SEND 00316 ?01011? - SEND with Immediate 00317 00318 For UD QP: 00319 the encoding depends on the values of bit[31] of the Q_key field in the Datagram Segment (see Table 39, ?Unreliable Datagram Segment Format - Pointers,? on page 101) of 00320 both the current WQE and the next WQE, as follows: 00321 00322 If the last WQE Q_Key bit[31] is clear and the next WQE Q_key bit[31] is set : 00323 ?01000? - SEND 00324 ?01001? - SEND with Immediate 00325 00326 otherwise (if the next WQE Q_key bit[31] is cleared, or the last WQE Q_Key bit[31] is set): 00327 ?01010? - SEND 00328 ?01011? - SEND with Immediate 00329 00330 All other opcode values are RESERVED, and will result in invalid operation execution. */ 00331 pseudo_bit_t reserved0[0x00001]; 00332 pseudo_bit_t nda_31_6[0x0001a]; /* Next WQE address, low 32 bit. WQE address must be aligned to 64-byte boundary (6 LSB are forced ZERO). */ 00333 /* -------------- */ 00334 pseudo_bit_t nds[0x00006]; /* Next WQE size in OctoWords (16 bytes). 00335 Zero value in NDS field signals end of WQEs? chain. 00336 */ 00337 pseudo_bit_t f[0x00001]; /* Fence bit. If set, next WQE will start execution only after all previous Read/Atomic WQEs complete. */ 00338 pseudo_bit_t always1[0x00001]; 00339 pseudo_bit_t reserved1[0x00018]; 00340 /* -------------- */ 00341 }; 00342 00343 /* Address Path */ 00344 00345 struct arbelprm_address_path_st { /* Little Endian */ 00346 pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ 00347 pseudo_bit_t reserved0[0x00011]; 00348 pseudo_bit_t port_number[0x00002]; /* Specific port associated with this QP/EE. 00349 1 - Port 1 00350 2 - Port 2 00351 other - reserved */ 00352 pseudo_bit_t reserved1[0x00006]; 00353 /* -------------- */ 00354 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 00355 pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 00356 pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 00357 pseudo_bit_t reserved2[0x00005]; 00358 pseudo_bit_t rnr_retry[0x00003]; /* RNR retry count (see C9-132 in IB spec Vol 1) 00359 0-6 - number of retries 00360 7 - infinite */ 00361 /* -------------- */ 00362 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 00363 pseudo_bit_t max_stat_rate[0x00003];/* Maximum static rate control. 00364 0 - 100% injection rate 00365 1 - 25% injection rate 00366 2 - 12.5% injection rate 00367 3 - 50% injection rate 00368 other - reserved */ 00369 pseudo_bit_t reserved3[0x00005]; 00370 pseudo_bit_t mgid_index[0x00006]; /* Index to port GID table */ 00371 pseudo_bit_t reserved4[0x00005]; 00372 pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. 00373 The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ 00374 /* -------------- */ 00375 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 00376 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 00377 pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 00378 /* -------------- */ 00379 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 00380 /* -------------- */ 00381 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 00382 /* -------------- */ 00383 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 00384 /* -------------- */ 00385 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ 00386 /* -------------- */ 00387 }; 00388 00389 /* HCA Command Register (HCR) */ 00390 00391 struct arbelprm_hca_command_register_st { /* Little Endian */ 00392 pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ 00393 /* -------------- */ 00394 pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ 00395 /* -------------- */ 00396 pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ 00397 /* -------------- */ 00398 pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ 00399 /* -------------- */ 00400 pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ 00401 /* -------------- */ 00402 pseudo_bit_t reserved0[0x00010]; 00403 pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ 00404 /* -------------- */ 00405 pseudo_bit_t opcode[0x0000c]; /* Command opcode */ 00406 pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ 00407 pseudo_bit_t reserved1[0x00006]; 00408 pseudo_bit_t e[0x00001]; /* Event Request 00409 0 - Don't report event (software will poll the GO bit) 00410 1 - Report event to EQ when the command completes */ 00411 pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) 00412 Software can write to the HCR only if Go bit is cleared. 00413 Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ 00414 pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) 00415 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ 00416 /* -------------- */ 00417 }; 00418 00419 /* CQ Doorbell */ 00420 00421 struct arbelprm_cq_cmd_doorbell_st { /* Little Endian */ 00422 pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ 00423 pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ 00424 0x0 - Reserved 00425 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. 00426 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. 00427 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated 00428 Other - Reserved */ 00429 pseudo_bit_t reserved0[0x00001]; 00430 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. 00431 This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited 00432 completion or Request notification for multiple completions doorbells after receiving completion notification. 00433 This field is initialized to Zero */ 00434 pseudo_bit_t reserved1[0x00002]; 00435 /* -------------- */ 00436 pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ 00437 /* -------------- */ 00438 }; 00439 00440 /* RD-send doorbell */ 00441 00442 struct arbelprm_rd_send_doorbell_st { /* Little Endian */ 00443 pseudo_bit_t reserved0[0x00008]; 00444 pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) 00445 Must be zero for Nop and Bind operations */ 00446 /* -------------- */ 00447 pseudo_bit_t reserved1[0x00008]; 00448 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 00449 /* -------------- */ 00450 struct arbelprm_send_doorbell_st send_doorbell;/* Send Parameters */ 00451 /* -------------- */ 00452 }; 00453 00454 /* Multicast Group Member QP */ 00455 00456 struct arbelprm_mgmqp_st { /* Little Endian */ 00457 pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ 00458 pseudo_bit_t reserved0[0x00007]; 00459 pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ 00460 /* -------------- */ 00461 }; 00462 00463 /* vsd */ 00464 00465 struct arbelprm_vsd_st { /* Little Endian */ 00466 pseudo_bit_t vsd_dw0[0x00020]; 00467 /* -------------- */ 00468 pseudo_bit_t vsd_dw1[0x00020]; 00469 /* -------------- */ 00470 pseudo_bit_t vsd_dw2[0x00020]; 00471 /* -------------- */ 00472 pseudo_bit_t vsd_dw3[0x00020]; 00473 /* -------------- */ 00474 pseudo_bit_t vsd_dw4[0x00020]; 00475 /* -------------- */ 00476 pseudo_bit_t vsd_dw5[0x00020]; 00477 /* -------------- */ 00478 pseudo_bit_t vsd_dw6[0x00020]; 00479 /* -------------- */ 00480 pseudo_bit_t vsd_dw7[0x00020]; 00481 /* -------------- */ 00482 pseudo_bit_t vsd_dw8[0x00020]; 00483 /* -------------- */ 00484 pseudo_bit_t vsd_dw9[0x00020]; 00485 /* -------------- */ 00486 pseudo_bit_t vsd_dw10[0x00020]; 00487 /* -------------- */ 00488 pseudo_bit_t vsd_dw11[0x00020]; 00489 /* -------------- */ 00490 pseudo_bit_t vsd_dw12[0x00020]; 00491 /* -------------- */ 00492 pseudo_bit_t vsd_dw13[0x00020]; 00493 /* -------------- */ 00494 pseudo_bit_t vsd_dw14[0x00020]; 00495 /* -------------- */ 00496 pseudo_bit_t vsd_dw15[0x00020]; 00497 /* -------------- */ 00498 pseudo_bit_t vsd_dw16[0x00020]; 00499 /* -------------- */ 00500 pseudo_bit_t vsd_dw17[0x00020]; 00501 /* -------------- */ 00502 pseudo_bit_t vsd_dw18[0x00020]; 00503 /* -------------- */ 00504 pseudo_bit_t vsd_dw19[0x00020]; 00505 /* -------------- */ 00506 pseudo_bit_t vsd_dw20[0x00020]; 00507 /* -------------- */ 00508 pseudo_bit_t vsd_dw21[0x00020]; 00509 /* -------------- */ 00510 pseudo_bit_t vsd_dw22[0x00020]; 00511 /* -------------- */ 00512 pseudo_bit_t vsd_dw23[0x00020]; 00513 /* -------------- */ 00514 pseudo_bit_t vsd_dw24[0x00020]; 00515 /* -------------- */ 00516 pseudo_bit_t vsd_dw25[0x00020]; 00517 /* -------------- */ 00518 pseudo_bit_t vsd_dw26[0x00020]; 00519 /* -------------- */ 00520 pseudo_bit_t vsd_dw27[0x00020]; 00521 /* -------------- */ 00522 pseudo_bit_t vsd_dw28[0x00020]; 00523 /* -------------- */ 00524 pseudo_bit_t vsd_dw29[0x00020]; 00525 /* -------------- */ 00526 pseudo_bit_t vsd_dw30[0x00020]; 00527 /* -------------- */ 00528 pseudo_bit_t vsd_dw31[0x00020]; 00529 /* -------------- */ 00530 pseudo_bit_t vsd_dw32[0x00020]; 00531 /* -------------- */ 00532 pseudo_bit_t vsd_dw33[0x00020]; 00533 /* -------------- */ 00534 pseudo_bit_t vsd_dw34[0x00020]; 00535 /* -------------- */ 00536 pseudo_bit_t vsd_dw35[0x00020]; 00537 /* -------------- */ 00538 pseudo_bit_t vsd_dw36[0x00020]; 00539 /* -------------- */ 00540 pseudo_bit_t vsd_dw37[0x00020]; 00541 /* -------------- */ 00542 pseudo_bit_t vsd_dw38[0x00020]; 00543 /* -------------- */ 00544 pseudo_bit_t vsd_dw39[0x00020]; 00545 /* -------------- */ 00546 pseudo_bit_t vsd_dw40[0x00020]; 00547 /* -------------- */ 00548 pseudo_bit_t vsd_dw41[0x00020]; 00549 /* -------------- */ 00550 pseudo_bit_t vsd_dw42[0x00020]; 00551 /* -------------- */ 00552 pseudo_bit_t vsd_dw43[0x00020]; 00553 /* -------------- */ 00554 pseudo_bit_t vsd_dw44[0x00020]; 00555 /* -------------- */ 00556 pseudo_bit_t vsd_dw45[0x00020]; 00557 /* -------------- */ 00558 pseudo_bit_t vsd_dw46[0x00020]; 00559 /* -------------- */ 00560 pseudo_bit_t vsd_dw47[0x00020]; 00561 /* -------------- */ 00562 pseudo_bit_t vsd_dw48[0x00020]; 00563 /* -------------- */ 00564 pseudo_bit_t vsd_dw49[0x00020]; 00565 /* -------------- */ 00566 pseudo_bit_t vsd_dw50[0x00020]; 00567 /* -------------- */ 00568 pseudo_bit_t vsd_dw51[0x00020]; 00569 /* -------------- */ 00570 pseudo_bit_t vsd_dw52[0x00020]; 00571 /* -------------- */ 00572 pseudo_bit_t vsd_dw53[0x00020]; 00573 /* -------------- */ 00574 pseudo_bit_t vsd_dw54[0x00020]; 00575 /* -------------- */ 00576 pseudo_bit_t vsd_dw55[0x00020]; 00577 /* -------------- */ 00578 }; 00579 00580 /* ACCESS_LAM_inject_errors */ 00581 00582 struct arbelprm_access_lam_inject_errors_st { /* Little Endian */ 00583 struct arbelprm_access_lam_inject_errors_input_parameter_st access_lam_inject_errors_input_parameter; 00584 /* -------------- */ 00585 struct arbelprm_access_lam_inject_errors_input_modifier_st access_lam_inject_errors_input_modifier; 00586 /* -------------- */ 00587 pseudo_bit_t reserved0[0x00020]; 00588 /* -------------- */ 00589 }; 00590 00591 /* Logical DIMM Information */ 00592 00593 struct arbelprm_dimminfo_st { /* Little Endian */ 00594 pseudo_bit_t dimmsize[0x00010]; /* Size of DIMM in units of 2^20 Bytes. This value is valid only when DIMMStatus is 0. */ 00595 pseudo_bit_t reserved0[0x00008]; 00596 pseudo_bit_t dimmstatus[0x00001]; /* DIMM Status 00597 0 - Enabled 00598 1 - Disabled 00599 */ 00600 pseudo_bit_t dh[0x00001]; /* When set, the DIMM is Hidden and can not be accessed from the PCI bus. */ 00601 pseudo_bit_t wo[0x00001]; /* When set, the DIMM is write only. 00602 If data integrity is configured (other than none), the DIMM must be 00603 only targeted by write transactions where the address and size are multiples of 16 bytes. */ 00604 pseudo_bit_t reserved1[0x00005]; 00605 /* -------------- */ 00606 pseudo_bit_t spd[0x00001]; /* 0 - DIMM SPD was read from DIMM 00607 1 - DIMM SPD was read from InfiniHost-III-EX NVMEM */ 00608 pseudo_bit_t sladr[0x00003]; /* SPD Slave Address 3 LSBits. 00609 Valid only if spd bit is 0. */ 00610 pseudo_bit_t sock_num[0x00002]; /* DIMM socket number (for double sided DIMM one of the two numbers will be reported) */ 00611 pseudo_bit_t syn[0x00004]; /* Error syndrome (valid regardless of status value) 00612 0 - DIMM has no error 00613 1 - SPD error (e.g. checksum error, no response, error while reading) 00614 2 - DIMM out of bounds (e.g. DIMM rows number is not between 7 and 14, DIMM type is not 2) 00615 3 - DIMM conflict (e.g. mix of registered and unbuffered DIMMs, CAS latency conflict) 00616 5 - DIMM size trimmed due to configuration (size exceeds) 00617 other - Error, reserved 00618 */ 00619 pseudo_bit_t reserved2[0x00016]; 00620 /* -------------- */ 00621 pseudo_bit_t reserved3[0x00040]; 00622 /* -------------- */ 00623 pseudo_bit_t dimm_start_adr_h[0x00020];/* DIMM memory start address [63:32]. This value is valid only when DIMMStatus is 0. */ 00624 /* -------------- */ 00625 pseudo_bit_t dimm_start_adr_l[0x00020];/* DIMM memory start address [31:0]. This value is valid only when DIMMStatus is 0. */ 00626 /* -------------- */ 00627 pseudo_bit_t reserved4[0x00040]; 00628 /* -------------- */ 00629 }; 00630 00631 /* UAR Parameters */ 00632 00633 struct arbelprm_uar_params_st { /* Little Endian */ 00634 pseudo_bit_t uar_base_addr_h[0x00020];/* UAR Base (pyhsical) Address [63:32] (QUERY_HCA only) */ 00635 /* -------------- */ 00636 pseudo_bit_t reserved0[0x00014]; 00637 pseudo_bit_t uar_base_addr_l[0x0000c];/* UAR Base (pyhsical) Address [31:20] (QUERY_HCA only) */ 00638 /* -------------- */ 00639 pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. 00640 Size of UAR Page is 4KB*2^UAR_Page_Size */ 00641 pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ 00642 pseudo_bit_t reserved1[0x00004]; 00643 pseudo_bit_t log_uar_entry_sz[0x00006];/* Size of UAR Context entry is 2^log_uar_sz in 4KByte pages */ 00644 pseudo_bit_t reserved2[0x0000a]; 00645 /* -------------- */ 00646 pseudo_bit_t reserved3[0x00020]; 00647 /* -------------- */ 00648 pseudo_bit_t uar_scratch_base_addr_h[0x00020];/* Base address of UAR scratchpad [63:32]. 00649 Number of entries in table is 2^log_max_uars. 00650 Table must be aligned to its size */ 00651 /* -------------- */ 00652 pseudo_bit_t uar_scratch_base_addr_l[0x00020];/* Base address of UAR scratchpad [31:0]. 00653 Number of entries in table is 2^log_max_uars. 00654 Table must be aligned to its size. */ 00655 /* -------------- */ 00656 pseudo_bit_t uar_context_base_addr_h[0x00020];/* Base address of UAR Context [63:32]. 00657 Number of entries in table is 2^log_max_uars. 00658 Table must be aligned to its size. */ 00659 /* -------------- */ 00660 pseudo_bit_t uar_context_base_addr_l[0x00020];/* Base address of UAR Context [31:0]. 00661 Number of entries in table is 2^log_max_uars. 00662 Table must be aligned to its size. */ 00663 /* -------------- */ 00664 }; 00665 00666 /* Translation and Protection Tables Parameters */ 00667 00668 struct arbelprm_tptparams_st { /* Little Endian */ 00669 pseudo_bit_t mpt_base_adr_h[0x00020];/* MPT - Memory Protection Table base physical address [63:32]. 00670 Entry size is 64 bytes. 00671 Table must be aligned to its size. 00672 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00673 /* -------------- */ 00674 pseudo_bit_t mpt_base_adr_l[0x00020];/* MPT - Memory Protection Table base physical address [31:0]. 00675 Entry size is 64 bytes. 00676 Table must be aligned to its size. 00677 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00678 /* -------------- */ 00679 pseudo_bit_t log_mpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the MPT table. */ 00680 pseudo_bit_t reserved0[0x00002]; 00681 pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - 00682 The field returned in RNR Naks generated when a page fault is detected. 00683 It has no effect when on-demand-paging is not used. */ 00684 pseudo_bit_t reserved1[0x00013]; 00685 /* -------------- */ 00686 pseudo_bit_t reserved2[0x00020]; 00687 /* -------------- */ 00688 pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. 00689 Table must be aligned to its size. 00690 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00691 /* -------------- */ 00692 pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. 00693 Table must be aligned to its size. 00694 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 00695 /* -------------- */ 00696 pseudo_bit_t reserved3[0x00040]; 00697 /* -------------- */ 00698 }; 00699 00700 /* Multicast Support Parameters */ 00701 00702 struct arbelprm_multicastparam_st { /* Little Endian */ 00703 pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. 00704 The base address must be aligned to the entry size. 00705 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 00706 /* -------------- */ 00707 pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. 00708 The base address must be aligned to the entry size. 00709 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 00710 /* -------------- */ 00711 pseudo_bit_t reserved0[0x00040]; 00712 /* -------------- */ 00713 pseudo_bit_t log_mc_table_entry_sz[0x00010];/* Log2 of the Size of multicast group member (MGM) entry. 00714 Must be greater than 5 (to allow CTRL and GID sections). 00715 That implies the number of QPs per MC table entry. */ 00716 pseudo_bit_t reserved1[0x00010]; 00717 /* -------------- */ 00718 pseudo_bit_t mc_table_hash_sz[0x00011];/* Number of entries in multicast DGID hash table (must be power of 2) 00719 INIT_HCA - the required number of entries 00720 QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ 00721 pseudo_bit_t reserved2[0x0000f]; 00722 /* -------------- */ 00723 pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ 00724 pseudo_bit_t reserved3[0x00013]; 00725 pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function 00726 0 - Default hash function 00727 other - reserved */ 00728 pseudo_bit_t reserved4[0x00005]; 00729 /* -------------- */ 00730 pseudo_bit_t reserved5[0x00020]; 00731 /* -------------- */ 00732 }; 00733 00734 /* QPC/EEC/CQC/EQC/RDB Parameters */ 00735 00736 struct arbelprm_qpcbaseaddr_st { /* Little Endian */ 00737 pseudo_bit_t reserved0[0x00080]; 00738 /* -------------- */ 00739 pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] 00740 Table must be aligned on its size */ 00741 /* -------------- */ 00742 pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ 00743 pseudo_bit_t reserved1[0x00002]; 00744 pseudo_bit_t qpc_base_addr_l[0x00019];/* QPC Base Address [31:7] 00745 Table must be aligned on its size */ 00746 /* -------------- */ 00747 pseudo_bit_t reserved2[0x00040]; 00748 /* -------------- */ 00749 pseudo_bit_t eec_base_addr_h[0x00020];/* EEC Base Address [63:32] 00750 Table must be aligned on its size. 00751 Address may be set to 0xFFFFFFFF if RD is not supported. */ 00752 /* -------------- */ 00753 pseudo_bit_t log_num_of_ee[0x00005];/* Log base 2 of number of supported EEs. */ 00754 pseudo_bit_t reserved3[0x00002]; 00755 pseudo_bit_t eec_base_addr_l[0x00019];/* EEC Base Address [31:7] 00756 Table must be aligned on its size 00757 Address may be set to 0xFFFFFFFF if RD is not supported. */ 00758 /* -------------- */ 00759 pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] 00760 Table must be aligned on its size 00761 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 00762 /* -------------- */ 00763 pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ 00764 pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] 00765 Table must be aligned on its size 00766 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 00767 /* -------------- */ 00768 pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] 00769 Table must be aligned on its size */ 00770 /* -------------- */ 00771 pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ 00772 pseudo_bit_t reserved4[0x00001]; 00773 pseudo_bit_t cqc_base_addr_l[0x0001a];/* CQC Base Address [31:6] 00774 Table must be aligned on its size */ 00775 /* -------------- */ 00776 pseudo_bit_t reserved5[0x00040]; 00777 /* -------------- */ 00778 pseudo_bit_t eqpc_base_addr_h[0x00020];/* Extended QPC Base Address [63:32] 00779 Table has same number of entries as QPC table. 00780 Table must be aligned to entry size. */ 00781 /* -------------- */ 00782 pseudo_bit_t eqpc_base_addr_l[0x00020];/* Extended QPC Base Address [31:0] 00783 Table has same number of entries as QPC table. 00784 Table must be aligned to entry size. */ 00785 /* -------------- */ 00786 pseudo_bit_t reserved6[0x00040]; 00787 /* -------------- */ 00788 pseudo_bit_t eeec_base_addr_h[0x00020];/* Extended EEC Base Address [63:32] 00789 Table has same number of entries as EEC table. 00790 Table must be aligned to entry size. 00791 Address may be set to 0xFFFFFFFF if RD is not supported. */ 00792 /* -------------- */ 00793 pseudo_bit_t eeec_base_addr_l[0x00020];/* Extended EEC Base Address [31:0] 00794 Table has same number of entries as EEC table. 00795 Table must be aligned to entry size. 00796 Address may be set to 0xFFFFFFFF if RD is not supported. */ 00797 /* -------------- */ 00798 pseudo_bit_t reserved7[0x00040]; 00799 /* -------------- */ 00800 pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] 00801 Address may be set to 0xFFFFFFFF if EQs are not supported. 00802 Table must be aligned to entry size. */ 00803 /* -------------- */ 00804 pseudo_bit_t log_num_eq[0x00004]; /* Log base 2 of number of supported EQs. 00805 Must be 6 or less in InfiniHost-III-EX. */ 00806 pseudo_bit_t reserved8[0x00002]; 00807 pseudo_bit_t eqc_base_addr_l[0x0001a];/* EQC Base Address [31:6] 00808 Address may be set to 0xFFFFFFFF if EQs are not supported. 00809 Table must be aligned to entry size. */ 00810 /* -------------- */ 00811 pseudo_bit_t reserved9[0x00040]; 00812 /* -------------- */ 00813 pseudo_bit_t rdb_base_addr_h[0x00020];/* Base address of table that holds remote read and remote atomic requests [63:32]. 00814 Address may be set to 0xFFFFFFFF if remote RDMA reads are not supported. 00815 Please refer to QP and EE chapter for further explanation on RDB allocation. */ 00816 /* -------------- */ 00817 pseudo_bit_t rdb_base_addr_l[0x00020];/* Base address of table that holds remote read and remote atomic requests [31:0]. 00818 Table must be aligned to RDB entry size (32 bytes). 00819 Address may be set to zero if remote RDMA reads are not supported. 00820 Please refer to QP and EE chapter for further explanation on RDB allocation. */ 00821 /* -------------- */ 00822 pseudo_bit_t reserved10[0x00040]; 00823 /* -------------- */ 00824 }; 00825 00826 /* Header_Log_Register */ 00827 00828 struct arbelprm_header_log_register_st { /* Little Endian */ 00829 pseudo_bit_t place_holder[0x00020]; 00830 /* -------------- */ 00831 pseudo_bit_t reserved0[0x00060]; 00832 /* -------------- */ 00833 }; 00834 00835 /* Performance Monitors */ 00836 00837 struct arbelprm_performance_monitors_st { /* Little Endian */ 00838 pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ 00839 pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ 00840 pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ 00841 pseudo_bit_t reserved0[0x00001]; 00842 pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00843 pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00844 pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 00845 pseudo_bit_t reserved1[0x00001]; 00846 pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00847 pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00848 pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 00849 pseudo_bit_t reserved2[0x00001]; 00850 pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00851 pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00852 pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 00853 pseudo_bit_t reserved3[0x00001]; 00854 pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ 00855 pseudo_bit_t reserved4[0x00003]; 00856 pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ 00857 pseudo_bit_t reserved5[0x00003]; 00858 /* -------------- */ 00859 pseudo_bit_t clock_counter[0x00020]; 00860 /* -------------- */ 00861 pseudo_bit_t event_counter1[0x00020]; 00862 /* -------------- */ 00863 pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ 00864 /* -------------- */ 00865 }; 00866 00867 /* Receive segment format */ 00868 00869 struct arbelprm_wqe_segment_ctrl_recv_st { /* Little Endian */ 00870 struct arbelprm_recv_wqe_segment_next_st wqe_segment_next; 00871 /* -------------- */ 00872 pseudo_bit_t reserved0[0x00002]; 00873 pseudo_bit_t reserved1[0x00001]; 00874 pseudo_bit_t reserved2[0x00001]; 00875 pseudo_bit_t reserved3[0x0001c]; 00876 /* -------------- */ 00877 pseudo_bit_t reserved4[0x00020]; 00878 /* -------------- */ 00879 }; 00880 00881 /* MLX WQE segment format */ 00882 00883 struct arbelprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ 00884 pseudo_bit_t reserved0[0x00002]; 00885 pseudo_bit_t e[0x00001]; /* WQE event */ 00886 pseudo_bit_t c[0x00001]; /* Create CQE (for "requested signalling" QP) */ 00887 pseudo_bit_t icrc[0x00002]; /* icrc field detemines what to do with the last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. Last dword must be 0x0. 1,2 - reserved. 3 - Leave last dword as is. Last dword must not be 0x0. */ 00888 pseudo_bit_t reserved1[0x00002]; 00889 pseudo_bit_t sl[0x00004]; 00890 pseudo_bit_t max_statrate[0x00004]; 00891 pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ 00892 pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ 00893 pseudo_bit_t reserved2[0x0000e]; 00894 /* -------------- */ 00895 pseudo_bit_t vcrc[0x00010]; /* Packet's VCRC (if not 0 - otherwise computed by HW) */ 00896 pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ 00897 /* -------------- */ 00898 pseudo_bit_t reserved3[0x00040]; 00899 /* -------------- */ 00900 }; 00901 00902 /* Send WQE segment format */ 00903 00904 struct arbelprm_send_wqe_segment_st { /* Little Endian */ 00905 struct arbelprm_wqe_segment_next_st wqe_segment_next;/* Send wqe segment next */ 00906 /* -------------- */ 00907 struct arbelprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ 00908 /* -------------- */ 00909 struct arbelprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ 00910 /* -------------- */ 00911 struct arbelprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ 00912 /* -------------- */ 00913 struct arbelprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ 00914 /* -------------- */ 00915 pseudo_bit_t reserved0[0x00180]; 00916 /* -------------- */ 00917 struct arbelprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ 00918 /* -------------- */ 00919 struct arbelprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ 00920 /* -------------- */ 00921 struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 00922 /* -------------- */ 00923 struct arbelprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ 00924 /* -------------- */ 00925 struct arbelprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ 00926 /* -------------- */ 00927 struct arbelprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ 00928 /* -------------- */ 00929 pseudo_bit_t reserved1[0x00200]; 00930 /* -------------- */ 00931 }; 00932 00933 /* QP and EE Context Entry */ 00934 00935 struct arbelprm_queue_pair_ee_context_entry_st { /* Little Endian */ 00936 pseudo_bit_t reserved0[0x00008]; 00937 pseudo_bit_t de[0x00001]; /* Send/Receive Descriptor Event enable - if set, events can be generated upon descriptors' completion on send/receive queue (controlled by E bit in WQE). Invalid in EE context */ 00938 pseudo_bit_t reserved1[0x00002]; 00939 pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) 00940 11-Migrated 00941 00-Armed 00942 01-Rearm 00943 10-Reserved 00944 Should be set to 11 for UD QPs and for QPs which do not support APM */ 00945 pseudo_bit_t reserved2[0x00003]; 00946 pseudo_bit_t st[0x00003]; /* Service type (invalid in EE context): 00947 000-Reliable Connection 00948 001-Unreliable Connection 00949 010-Reliable Datagram 00950 011-Unreliable Datagram 00951 111-MLX transport (raw bits injection). Used for management QPs and RAW */ 00952 pseudo_bit_t reserved3[0x00009]; 00953 pseudo_bit_t state[0x00004]; /* QP/EE state: 00954 0 - RST 00955 1 - INIT 00956 2 - RTR 00957 3 - RTS 00958 4 - SQEr 00959 5 - SQD (Send Queue Drained) 00960 6 - ERR 00961 7 - Send Queue Draining 00962 8 - Reserved 00963 9 - Suspended 00964 A- F - Reserved 00965 (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ 00966 /* -------------- */ 00967 pseudo_bit_t reserved4[0x00020]; 00968 /* -------------- */ 00969 pseudo_bit_t sched_queue[0x00004]; /* Schedule queue to be used for WQE scheduling to execution. Determines QOS for this QP. */ 00970 pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ 00971 pseudo_bit_t reserved5[0x00003]; 00972 pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. 00973 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 00974 pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ 00975 pseudo_bit_t reserved6[0x00001]; 00976 pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. 00977 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 00978 pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ 00979 pseudo_bit_t reserved7[0x00001]; 00980 pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. 00981 Must be equal to MTU for UD and MLX QPs. */ 00982 pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): 00983 0x1 - 256 bytes 00984 0x2 - 512 00985 0x3 - 1024 00986 0x4 - 2048 00987 other - reserved 00988 00989 Should be configured to 0x4 for UD and MLX QPs. */ 00990 /* -------------- */ 00991 pseudo_bit_t usr_page[0x00018]; /* QP (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */ 00992 pseudo_bit_t reserved8[0x00008]; 00993 /* -------------- */ 00994 pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained 00995 This field is valid for QUERY and ERR2RST commands only. */ 00996 pseudo_bit_t reserved9[0x00008]; 00997 /* -------------- */ 00998 pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ 00999 pseudo_bit_t reserved10[0x00008]; 01000 /* -------------- */ 01001 pseudo_bit_t reserved11[0x00040]; 01002 /* -------------- */ 01003 struct arbelprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ 01004 /* -------------- */ 01005 struct arbelprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ 01006 /* -------------- */ 01007 pseudo_bit_t rdd[0x00018]; /* Reliable Datagram Domain */ 01008 pseudo_bit_t reserved12[0x00008]; 01009 /* -------------- */ 01010 pseudo_bit_t pd[0x00018]; /* QP protection domain. Not valid (reserved) in EE context. */ 01011 pseudo_bit_t reserved13[0x00008]; 01012 /* -------------- */ 01013 pseudo_bit_t wqe_base_adr_h[0x00020];/* Bits 63:32 of WQE address for both SQ and RQ. 01014 Reserved for EE context. */ 01015 /* -------------- */ 01016 pseudo_bit_t wqe_lkey[0x00020]; /* memory key (L-Key) to be used to access WQEs. Not valid (reserved) in EE context. */ 01017 /* -------------- */ 01018 pseudo_bit_t reserved14[0x00003]; 01019 pseudo_bit_t ssc[0x00001]; /* Send Signaled Completion 01020 1 - all send WQEs generate CQEs. 01021 0 - only send WQEs with C bit set generate completion. 01022 Not valid (reserved) in EE context. */ 01023 pseudo_bit_t sic[0x00001]; /* If set - Ignore end to end credits on send queue. Not valid (reserved) in EE context. */ 01024 pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). 01025 The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ 01026 pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). 01027 The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ 01028 pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ 01029 pseudo_bit_t reserved15[0x00001]; 01030 pseudo_bit_t sae[0x00001]; /* If set - Atomic operations enabled on send queue. Not valid (reserved) in EE context. */ 01031 pseudo_bit_t swe[0x00001]; /* If set - RDMA - write enabled on send queue. Not valid (reserved) in EE context. */ 01032 pseudo_bit_t sre[0x00001]; /* If set - RDMA - read enabled on send queue. Not valid (reserved) in EE context. */ 01033 pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ 01034 pseudo_bit_t reserved16[0x00002]; 01035 pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ 01036 pseudo_bit_t flight_lim[0x00004]; /* Number of outstanding (in-flight) messages on the wire allowed for this send queue. 01037 Number of outstanding messages is 2^Flight_Lim. 01038 Use 0xF for unlimited number of outstanding messages. */ 01039 pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ 01040 /* -------------- */ 01041 pseudo_bit_t reserved17[0x00020]; 01042 /* -------------- */ 01043 pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ 01044 pseudo_bit_t reserved18[0x00008]; 01045 /* -------------- */ 01046 pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ 01047 pseudo_bit_t reserved19[0x00008]; 01048 /* -------------- */ 01049 pseudo_bit_t reserved20[0x00006]; 01050 pseudo_bit_t snd_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */ 01051 /* -------------- */ 01052 pseudo_bit_t snd_db_record_index[0x00020];/* Index in the UAR Context Table Entry. 01053 HW uses this index as an offset from the UAR Context Table Entry in order to read this SQ doorbell record. 01054 The entry is obtained via the usr_page field. 01055 Not valid for EE. */ 01056 /* -------------- */ 01057 pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ 01058 pseudo_bit_t reserved21[0x00008]; 01059 /* -------------- */ 01060 pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ 01061 pseudo_bit_t reserved22[0x00008]; 01062 /* -------------- */ 01063 pseudo_bit_t reserved23[0x00003]; 01064 pseudo_bit_t rsc[0x00001]; /* 1 - all receive WQEs generate CQEs. 01065 0 - only receive WQEs with C bit set generate completion. 01066 Not valid (reserved) in EE context. 01067 */ 01068 pseudo_bit_t ric[0x00001]; /* Invalid Credits. 01069 1 - place "Invalid Credits" to ACKs sent from this queue. 01070 0 - ACKs report the actual number of end to end credits on the connection. 01071 Not valid (reserved) in EE context. 01072 Must be set to 1 on QPs which are attached to SRQ. */ 01073 pseudo_bit_t reserved24[0x00008]; 01074 pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ 01075 pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ 01076 pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ 01077 pseudo_bit_t reserved25[0x00005]; 01078 pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. 01079 Must be 0 for EE context. */ 01080 pseudo_bit_t reserved26[0x00008]; 01081 /* -------------- */ 01082 pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ 01083 pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). 01084 Not valid (reserved) in EE context. */ 01085 pseudo_bit_t reserved27[0x00003]; 01086 /* -------------- */ 01087 pseudo_bit_t reserved28[0x00005]; 01088 pseudo_bit_t ra_buff_indx[0x0001b]; /* Index to outstanding read/atomic buffer. 01089 This field constructs the address to the RDB for maintaining the incoming RDMA read and atomic requests. */ 01090 /* -------------- */ 01091 pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ 01092 pseudo_bit_t reserved29[0x00008]; 01093 /* -------------- */ 01094 pseudo_bit_t reserved30[0x00006]; 01095 pseudo_bit_t rcv_wqe_base_adr_l[0x0001a];/* While opening (creating) the WQ, this field should contain the address of first descriptor to be posted. Not valid (reserved) in EE context. */ 01096 /* -------------- */ 01097 pseudo_bit_t rcv_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. 01098 HW uses this index as an offset from the UAR Context Table Entry in order to read this RQ doorbell record. 01099 The entry is obtained via the usr_page field. 01100 Not valid for EE. */ 01101 /* -------------- */ 01102 pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. 01103 On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. 01104 Not valid (reserved) in EE context. */ 01105 /* -------------- */ 01106 pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. 01107 SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ 01108 pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ 01109 pseudo_bit_t reserved31[0x00007]; 01110 /* -------------- */ 01111 pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ 01112 pseudo_bit_t reserved32[0x00008]; 01113 /* -------------- */ 01114 pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 01115 Must be 0x0 in SQ initialization. 01116 (QUERY_QPEE only). */ 01117 pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. 01118 Must be 0x0 in RQ initialization. 01119 (QUERY_QPEE only). */ 01120 /* -------------- */ 01121 pseudo_bit_t reserved33[0x00040]; 01122 /* -------------- */ 01123 }; 01124 01125 /* Clear Interrupt [63:0] */ 01126 01127 struct arbelprm_clr_int_st { /* Little Endian */ 01128 pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] 01129 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 01130 This register is write-only. Reading from this register will cause undefined result 01131 */ 01132 /* -------------- */ 01133 pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] 01134 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 01135 This register is write-only. Reading from this register will cause undefined result */ 01136 /* -------------- */ 01137 }; 01138 01139 /* EQ_Arm_DB_Region */ 01140 01141 struct arbelprm_eq_arm_db_region_st { /* Little Endian */ 01142 pseudo_bit_t eq_x_arm_h[0x00020]; /* EQ[63:32] X state. 01143 This register is used to Arm EQs when setting the appropriate bits. */ 01144 /* -------------- */ 01145 pseudo_bit_t eq_x_arm_l[0x00020]; /* EQ[31:0] X state. 01146 This register is used to Arm EQs when setting the appropriate bits. */ 01147 /* -------------- */ 01148 }; 01149 01150 /* EQ Set CI DBs Table */ 01151 01152 struct arbelprm_eq_set_ci_table_st { /* Little Endian */ 01153 pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ 01154 /* -------------- */ 01155 pseudo_bit_t reserved0[0x00020]; 01156 /* -------------- */ 01157 pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ 01158 /* -------------- */ 01159 pseudo_bit_t reserved1[0x00020]; 01160 /* -------------- */ 01161 pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ 01162 /* -------------- */ 01163 pseudo_bit_t reserved2[0x00020]; 01164 /* -------------- */ 01165 pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ 01166 /* -------------- */ 01167 pseudo_bit_t reserved3[0x00020]; 01168 /* -------------- */ 01169 pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ 01170 /* -------------- */ 01171 pseudo_bit_t reserved4[0x00020]; 01172 /* -------------- */ 01173 pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ 01174 /* -------------- */ 01175 pseudo_bit_t reserved5[0x00020]; 01176 /* -------------- */ 01177 pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ 01178 /* -------------- */ 01179 pseudo_bit_t reserved6[0x00020]; 01180 /* -------------- */ 01181 pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ 01182 /* -------------- */ 01183 pseudo_bit_t reserved7[0x00020]; 01184 /* -------------- */ 01185 pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ 01186 /* -------------- */ 01187 pseudo_bit_t reserved8[0x00020]; 01188 /* -------------- */ 01189 pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ 01190 /* -------------- */ 01191 pseudo_bit_t reserved9[0x00020]; 01192 /* -------------- */ 01193 pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ 01194 /* -------------- */ 01195 pseudo_bit_t reserved10[0x00020]; 01196 /* -------------- */ 01197 pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ 01198 /* -------------- */ 01199 pseudo_bit_t reserved11[0x00020]; 01200 /* -------------- */ 01201 pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ 01202 /* -------------- */ 01203 pseudo_bit_t reserved12[0x00020]; 01204 /* -------------- */ 01205 pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ 01206 /* -------------- */ 01207 pseudo_bit_t reserved13[0x00020]; 01208 /* -------------- */ 01209 pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ 01210 /* -------------- */ 01211 pseudo_bit_t reserved14[0x00020]; 01212 /* -------------- */ 01213 pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ 01214 /* -------------- */ 01215 pseudo_bit_t reserved15[0x00020]; 01216 /* -------------- */ 01217 pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ 01218 /* -------------- */ 01219 pseudo_bit_t reserved16[0x00020]; 01220 /* -------------- */ 01221 pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ 01222 /* -------------- */ 01223 pseudo_bit_t reserved17[0x00020]; 01224 /* -------------- */ 01225 pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ 01226 /* -------------- */ 01227 pseudo_bit_t reserved18[0x00020]; 01228 /* -------------- */ 01229 pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ 01230 /* -------------- */ 01231 pseudo_bit_t reserved19[0x00020]; 01232 /* -------------- */ 01233 pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ 01234 /* -------------- */ 01235 pseudo_bit_t reserved20[0x00020]; 01236 /* -------------- */ 01237 pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ 01238 /* -------------- */ 01239 pseudo_bit_t reserved21[0x00020]; 01240 /* -------------- */ 01241 pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ 01242 /* -------------- */ 01243 pseudo_bit_t reserved22[0x00020]; 01244 /* -------------- */ 01245 pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ 01246 /* -------------- */ 01247 pseudo_bit_t reserved23[0x00020]; 01248 /* -------------- */ 01249 pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ 01250 /* -------------- */ 01251 pseudo_bit_t reserved24[0x00020]; 01252 /* -------------- */ 01253 pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ 01254 /* -------------- */ 01255 pseudo_bit_t reserved25[0x00020]; 01256 /* -------------- */ 01257 pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ 01258 /* -------------- */ 01259 pseudo_bit_t reserved26[0x00020]; 01260 /* -------------- */ 01261 pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ 01262 /* -------------- */ 01263 pseudo_bit_t reserved27[0x00020]; 01264 /* -------------- */ 01265 pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ 01266 /* -------------- */ 01267 pseudo_bit_t reserved28[0x00020]; 01268 /* -------------- */ 01269 pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ 01270 /* -------------- */ 01271 pseudo_bit_t reserved29[0x00020]; 01272 /* -------------- */ 01273 pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ 01274 /* -------------- */ 01275 pseudo_bit_t reserved30[0x00020]; 01276 /* -------------- */ 01277 pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ 01278 /* -------------- */ 01279 pseudo_bit_t reserved31[0x00020]; 01280 /* -------------- */ 01281 pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ 01282 /* -------------- */ 01283 pseudo_bit_t reserved32[0x00020]; 01284 /* -------------- */ 01285 pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ 01286 /* -------------- */ 01287 pseudo_bit_t reserved33[0x00020]; 01288 /* -------------- */ 01289 pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ 01290 /* -------------- */ 01291 pseudo_bit_t reserved34[0x00020]; 01292 /* -------------- */ 01293 pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ 01294 /* -------------- */ 01295 pseudo_bit_t reserved35[0x00020]; 01296 /* -------------- */ 01297 pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ 01298 /* -------------- */ 01299 pseudo_bit_t reserved36[0x00020]; 01300 /* -------------- */ 01301 pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ 01302 /* -------------- */ 01303 pseudo_bit_t reserved37[0x00020]; 01304 /* -------------- */ 01305 pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ 01306 /* -------------- */ 01307 pseudo_bit_t reserved38[0x00020]; 01308 /* -------------- */ 01309 pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ 01310 /* -------------- */ 01311 pseudo_bit_t reserved39[0x00020]; 01312 /* -------------- */ 01313 pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ 01314 /* -------------- */ 01315 pseudo_bit_t reserved40[0x00020]; 01316 /* -------------- */ 01317 pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ 01318 /* -------------- */ 01319 pseudo_bit_t reserved41[0x00020]; 01320 /* -------------- */ 01321 pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ 01322 /* -------------- */ 01323 pseudo_bit_t reserved42[0x00020]; 01324 /* -------------- */ 01325 pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ 01326 /* -------------- */ 01327 pseudo_bit_t reserved43[0x00020]; 01328 /* -------------- */ 01329 pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ 01330 /* -------------- */ 01331 pseudo_bit_t reserved44[0x00020]; 01332 /* -------------- */ 01333 pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ 01334 /* -------------- */ 01335 pseudo_bit_t reserved45[0x00020]; 01336 /* -------------- */ 01337 pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ 01338 /* -------------- */ 01339 pseudo_bit_t reserved46[0x00020]; 01340 /* -------------- */ 01341 pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ 01342 /* -------------- */ 01343 pseudo_bit_t reserved47[0x00020]; 01344 /* -------------- */ 01345 pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ 01346 /* -------------- */ 01347 pseudo_bit_t reserved48[0x00020]; 01348 /* -------------- */ 01349 pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ 01350 /* -------------- */ 01351 pseudo_bit_t reserved49[0x00020]; 01352 /* -------------- */ 01353 pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ 01354 /* -------------- */ 01355 pseudo_bit_t reserved50[0x00020]; 01356 /* -------------- */ 01357 pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ 01358 /* -------------- */ 01359 pseudo_bit_t reserved51[0x00020]; 01360 /* -------------- */ 01361 pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ 01362 /* -------------- */ 01363 pseudo_bit_t reserved52[0x00020]; 01364 /* -------------- */ 01365 pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ 01366 /* -------------- */ 01367 pseudo_bit_t reserved53[0x00020]; 01368 /* -------------- */ 01369 pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ 01370 /* -------------- */ 01371 pseudo_bit_t reserved54[0x00020]; 01372 /* -------------- */ 01373 pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ 01374 /* -------------- */ 01375 pseudo_bit_t reserved55[0x00020]; 01376 /* -------------- */ 01377 pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ 01378 /* -------------- */ 01379 pseudo_bit_t reserved56[0x00020]; 01380 /* -------------- */ 01381 pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ 01382 /* -------------- */ 01383 pseudo_bit_t reserved57[0x00020]; 01384 /* -------------- */ 01385 pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ 01386 /* -------------- */ 01387 pseudo_bit_t reserved58[0x00020]; 01388 /* -------------- */ 01389 pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ 01390 /* -------------- */ 01391 pseudo_bit_t reserved59[0x00020]; 01392 /* -------------- */ 01393 pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ 01394 /* -------------- */ 01395 pseudo_bit_t reserved60[0x00020]; 01396 /* -------------- */ 01397 pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ 01398 /* -------------- */ 01399 pseudo_bit_t reserved61[0x00020]; 01400 /* -------------- */ 01401 pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ 01402 /* -------------- */ 01403 pseudo_bit_t reserved62[0x00020]; 01404 /* -------------- */ 01405 pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ 01406 /* -------------- */ 01407 pseudo_bit_t reserved63[0x00020]; 01408 /* -------------- */ 01409 }; 01410 01411 /* InfiniHost-III-EX Configuration Registers */ 01412 01413 struct arbelprm_configuration_registers_st { /* Little Endian */ 01414 pseudo_bit_t reserved0[0x403400]; 01415 /* -------------- */ 01416 struct arbelprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ 01417 /* -------------- */ 01418 pseudo_bit_t reserved1[0x3fcb20]; 01419 /* -------------- */ 01420 }; 01421 01422 /* QP_DB_Record */ 01423 01424 struct arbelprm_qp_db_record_st { /* Little Endian */ 01425 pseudo_bit_t counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ 01426 pseudo_bit_t reserved0[0x00010]; 01427 /* -------------- */ 01428 pseudo_bit_t reserved1[0x00005]; 01429 pseudo_bit_t res[0x00003]; /* 0x3 for SQ 01430 0x4 for RQ 01431 0x5 for SRQ */ 01432 pseudo_bit_t qp_number[0x00018]; /* QP number */ 01433 /* -------------- */ 01434 }; 01435 01436 /* CQ_ARM_DB_Record */ 01437 01438 struct arbelprm_cq_arm_db_record_st { /* Little Endian */ 01439 pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ 01440 /* -------------- */ 01441 pseudo_bit_t cmd[0x00003]; /* 0x0 - No command 01442 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. 01443 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. 01444 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated 01445 Other - Reserved */ 01446 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ 01447 pseudo_bit_t res[0x00003]; /* Must be 0x2 */ 01448 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 01449 /* -------------- */ 01450 }; 01451 01452 /* CQ_CI_DB_Record */ 01453 01454 struct arbelprm_cq_ci_db_record_st { /* Little Endian */ 01455 pseudo_bit_t counter[0x00020]; /* CQ counter */ 01456 /* -------------- */ 01457 pseudo_bit_t reserved0[0x00005]; 01458 pseudo_bit_t res[0x00003]; /* Must be 0x1 */ 01459 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 01460 /* -------------- */ 01461 }; 01462 01463 /* Virtual_Physical_Mapping */ 01464 01465 struct arbelprm_virtual_physical_mapping_st { /* Little Endian */ 01466 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ 01467 /* -------------- */ 01468 pseudo_bit_t reserved0[0x0000c]; 01469 pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ 01470 /* -------------- */ 01471 pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ 01472 /* -------------- */ 01473 pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ 01474 pseudo_bit_t reserved1[0x00006]; 01475 pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ 01476 /* -------------- */ 01477 }; 01478 01479 /* MOD_STAT_CFG */ 01480 01481 struct arbelprm_mod_stat_cfg_st { /* Little Endian */ 01482 pseudo_bit_t log_max_srqs[0x00005]; /* Log (base 2) of the number of SRQs to allocate (0 if no SRQs are required), valid only if srq bit is set. */ 01483 pseudo_bit_t reserved0[0x00001]; 01484 pseudo_bit_t srq[0x00001]; /* When set SRQs are supported */ 01485 pseudo_bit_t srq_m[0x00001]; /* Modify SRQ parameters */ 01486 pseudo_bit_t reserved1[0x00018]; 01487 /* -------------- */ 01488 pseudo_bit_t reserved2[0x007e0]; 01489 /* -------------- */ 01490 }; 01491 01492 /* SRQ Context */ 01493 01494 struct arbelprm_srq_context_st { /* Little Endian */ 01495 pseudo_bit_t srqn[0x00018]; /* SRQ number */ 01496 pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. 01497 Maximum value is 0x10, i.e. 16M WQEs. */ 01498 pseudo_bit_t state[0x00004]; /* SRQ State: 01499 1111 - SW Ownership 01500 0000 - HW Ownership 01501 0001 - Error 01502 Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 01503 /* -------------- */ 01504 pseudo_bit_t l_key[0x00020]; /* memory key (L-Key) to be used to access WQEs. */ 01505 /* -------------- */ 01506 pseudo_bit_t srq_db_record_index[0x00020];/* Index in the UAR Context Table Entry containing the doorbell record for the receive queue. 01507 HW uses this index as an offset from the UAR Context Table Entry in order to read this SRQ doorbell record. 01508 The entry is obtained via the usr_page field. */ 01509 /* -------------- */ 01510 pseudo_bit_t usr_page[0x00018]; /* Index (offset) of user page allocated for this SRQ (see "non_privileged Access to the HCA Hardware"). Not valid (reserved) in EE context. */ 01511 pseudo_bit_t reserved0[0x00005]; 01512 pseudo_bit_t log_rq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ 01513 /* -------------- */ 01514 pseudo_bit_t wqe_addr_h[0x00020]; /* Bits 63:32 of WQE address (WQE base address) */ 01515 /* -------------- */ 01516 pseudo_bit_t reserved1[0x00006]; 01517 pseudo_bit_t srq_wqe_base_adr_l[0x0001a];/* While opening (creating) the SRQ, this field should contain the address of first descriptor to be posted. */ 01518 /* -------------- */ 01519 pseudo_bit_t pd[0x00018]; /* SRQ protection domain. */ 01520 pseudo_bit_t reserved2[0x00008]; 01521 /* -------------- */ 01522 pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. 01523 Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 01524 pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then a SRQ limit event is fired and the LWM is set to zero. */ 01525 /* -------------- */ 01526 pseudo_bit_t srq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 01527 Must be 0x0 in SRQ initialization. 01528 (QUERY_SRQ only). */ 01529 pseudo_bit_t reserved3[0x00010]; 01530 /* -------------- */ 01531 pseudo_bit_t reserved4[0x00060]; 01532 /* -------------- */ 01533 }; 01534 01535 /* PBL */ 01536 01537 struct arbelprm_pbl_st { /* Little Endian */ 01538 pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ 01539 /* -------------- */ 01540 pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ 01541 /* -------------- */ 01542 pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ 01543 /* -------------- */ 01544 pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ 01545 /* -------------- */ 01546 pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ 01547 /* -------------- */ 01548 pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ 01549 /* -------------- */ 01550 pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ 01551 /* -------------- */ 01552 pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ 01553 /* -------------- */ 01554 }; 01555 01556 /* Performance Counters */ 01557 01558 struct arbelprm_performance_counters_st { /* Little Endian */ 01559 pseudo_bit_t sqpc_access_cnt[0x00020];/* SQPC cache access count */ 01560 /* -------------- */ 01561 pseudo_bit_t sqpc_miss_cnt[0x00020];/* SQPC cache miss count */ 01562 /* -------------- */ 01563 pseudo_bit_t reserved0[0x00040]; 01564 /* -------------- */ 01565 pseudo_bit_t rqpc_access_cnt[0x00020];/* RQPC cache access count */ 01566 /* -------------- */ 01567 pseudo_bit_t rqpc_miss_cnt[0x00020];/* RQPC cache miss count */ 01568 /* -------------- */ 01569 pseudo_bit_t reserved1[0x00040]; 01570 /* -------------- */ 01571 pseudo_bit_t cqc_access_cnt[0x00020];/* CQC cache access count */ 01572 /* -------------- */ 01573 pseudo_bit_t cqc_miss_cnt[0x00020]; /* CQC cache miss count */ 01574 /* -------------- */ 01575 pseudo_bit_t reserved2[0x00040]; 01576 /* -------------- */ 01577 pseudo_bit_t tpt_access_cnt[0x00020];/* TPT cache access count */ 01578 /* -------------- */ 01579 pseudo_bit_t mpt_miss_cnt[0x00020]; /* MPT cache miss count */ 01580 /* -------------- */ 01581 pseudo_bit_t mtt_miss_cnt[0x00020]; /* MTT cache miss count */ 01582 /* -------------- */ 01583 pseudo_bit_t reserved3[0x00620]; 01584 /* -------------- */ 01585 }; 01586 01587 /* Transport and CI Error Counters */ 01588 01589 struct arbelprm_transport_and_ci_error_counters_st { /* Little Endian */ 01590 pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ 01591 /* -------------- */ 01592 pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ 01593 /* -------------- */ 01594 pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ 01595 /* -------------- */ 01596 pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ 01597 /* -------------- */ 01598 pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ 01599 /* -------------- */ 01600 pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ 01601 /* -------------- */ 01602 pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ 01603 /* -------------- */ 01604 pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ 01605 /* -------------- */ 01606 pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. 01607 Incremented each time a CQE with error is generated */ 01608 /* -------------- */ 01609 pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. 01610 Incremented each time a CQE with error is generated */ 01611 /* -------------- */ 01612 pseudo_bit_t reserved0[0x00020]; 01613 /* -------------- */ 01614 pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ 01615 /* -------------- */ 01616 pseudo_bit_t reserved1[0x00020]; 01617 /* -------------- */ 01618 pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ 01619 /* -------------- */ 01620 pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ 01621 /* -------------- */ 01622 pseudo_bit_t reserved2[0x00040]; 01623 /* -------------- */ 01624 pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors 01625 NAK-Invalid Request on: 01626 1. Unsupported OpCode: Responder detected an unsupported OpCode. 01627 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such 01628 as a missing "Last" packet. 01629 Note: there is no PSN error, thus this does not indicate a dropped packet. */ 01630 /* -------------- */ 01631 pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. 01632 NAK may or may not be sent. 01633 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): 01634 Inbound request OpCode was either reserved, or was for a function not supported by this 01635 QP. (E.g. RDMA or ATOMIC on QP not set up for this). 01636 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. 01637 3. Too many RDMA READ or ATOMIC Requests: There were more requests received 01638 and not ACKed than allowed for the connection. 01639 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder 01640 detected an error in the sequence of OpCodes; a missing "Last" packet 01641 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder 01642 detected an error in the sequence of OpCodes; a missing "First" packet 01643 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able 01644 buffer space. 01645 7. Length error: RDMA WRITE request message contained too much or too little pay-load 01646 data compared to the DMA length advertised in the first or only packet. 01647 8. Length error: Payload length was not consistent with the opcode: 01648 a: 0 byte <= "only" <= PMTU bytes 01649 b: ("first" or "middle") == PMTU bytes 01650 c: 1byte <= "last" <= PMTU bytes 01651 9. Length error: Inbound message exceeded the size supported by the CA port. */ 01652 /* -------------- */ 01653 pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. 01654 NAK-Remote Access Error on: 01655 R_Key Violation: Responder detected an invalid R_Key while executing an RDMA 01656 Request. */ 01657 /* -------------- */ 01658 pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. 01659 R_Key Violation Responder detected an R_Key violation while executing an RDMA 01660 request. 01661 NAK may or may not be sent. */ 01662 /* -------------- */ 01663 pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. 01664 NAK-Remote Operation Error on: 01665 Remote Operation Error: Responder encountered an error, (local to the responder), 01666 which prevented it from completing the request. */ 01667 /* -------------- */ 01668 pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. 01669 NAK-Remote Operation Error on: 01670 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing 01671 the packet. 01672 2. Remote Operation Error: Responder encountered an error, (local to the responder), 01673 which prevented it from completing the request. */ 01674 /* -------------- */ 01675 pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ 01676 /* -------------- */ 01677 pseudo_bit_t reserved3[0x00020]; 01678 /* -------------- */ 01679 pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ 01680 /* -------------- */ 01681 pseudo_bit_t reserved4[0x00020]; 01682 /* -------------- */ 01683 pseudo_bit_t sq_num_lrdve[0x00020]; /* Requester - number of local RDD violation errors */ 01684 /* -------------- */ 01685 pseudo_bit_t rq_num_rirdre[0x00020];/* Responder - number of remote invalid RD request errors */ 01686 /* -------------- */ 01687 pseudo_bit_t reserved5[0x00040]; 01688 /* -------------- */ 01689 pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ 01690 /* -------------- */ 01691 pseudo_bit_t reserved6[0x00020]; 01692 /* -------------- */ 01693 pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ 01694 /* -------------- */ 01695 pseudo_bit_t reserved7[0x00020]; 01696 /* -------------- */ 01697 pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ 01698 /* -------------- */ 01699 pseudo_bit_t reserved8[0x00380]; 01700 /* -------------- */ 01701 pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ 01702 /* -------------- */ 01703 pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ 01704 /* -------------- */ 01705 pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ 01706 /* -------------- */ 01707 pseudo_bit_t reserved9[0x00020]; 01708 /* -------------- */ 01709 pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ 01710 /* -------------- */ 01711 pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ 01712 /* -------------- */ 01713 pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ 01714 /* -------------- */ 01715 pseudo_bit_t reserved10[0x00020]; 01716 /* -------------- */ 01717 pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ 01718 /* -------------- */ 01719 pseudo_bit_t reserved11[0x003e0]; 01720 /* -------------- */ 01721 pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ 01722 /* -------------- */ 01723 pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ 01724 /* -------------- */ 01725 pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ 01726 /* -------------- */ 01727 pseudo_bit_t reserved12[0x002a0]; 01728 /* -------------- */ 01729 }; 01730 01731 /* Event_data Field - HCR Completion Event */ 01732 01733 struct arbelprm_hcr_completion_event_st { /* Little Endian */ 01734 pseudo_bit_t token[0x00010]; /* HCR Token */ 01735 pseudo_bit_t reserved0[0x00010]; 01736 /* -------------- */ 01737 pseudo_bit_t reserved1[0x00020]; 01738 /* -------------- */ 01739 pseudo_bit_t status[0x00008]; /* HCR Status */ 01740 pseudo_bit_t reserved2[0x00018]; 01741 /* -------------- */ 01742 pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ 01743 /* -------------- */ 01744 pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ 01745 /* -------------- */ 01746 pseudo_bit_t reserved3[0x00020]; 01747 /* -------------- */ 01748 }; 01749 01750 /* Completion with Error CQE */ 01751 01752 struct arbelprm_completion_with_error_st { /* Little Endian */ 01753 pseudo_bit_t myqpn[0x00018]; /* Indicates the QP for which completion is being reported */ 01754 pseudo_bit_t reserved0[0x00008]; 01755 /* -------------- */ 01756 pseudo_bit_t reserved1[0x00060]; 01757 /* -------------- */ 01758 pseudo_bit_t reserved2[0x00010]; 01759 pseudo_bit_t vendor_code[0x00008]; 01760 pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: 01761 0x01 - Local Length Error 01762 0x02 - Local QP Operation Error 01763 0x03 - Local EE Context Operation Error 01764 0x04 - Local Protection Error 01765 0x05 - Work Request Flushed Error 01766 0x06 - Memory Window Bind Error 01767 0x10 - Bad Response Error 01768 0x11 - Local Access Error 01769 0x12 - Remote Invalid Request Error 01770 0x13 - Remote Access Error 01771 0x14 - Remote Operation Error 01772 0x15 - Transport Retry Counter Exceeded 01773 0x16 - RNR Retry Counter Exceeded 01774 0x20 - Local RDD Violation Error 01775 0x21 - Remote Invalid RD Request 01776 0x22 - Remote Aborted Error 01777 0x23 - Invalid EE Context Number 01778 0x24 - Invalid EE Context State 01779 other - Reserved 01780 Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ 01781 /* -------------- */ 01782 pseudo_bit_t reserved3[0x00020]; 01783 /* -------------- */ 01784 pseudo_bit_t reserved4[0x00006]; 01785 pseudo_bit_t wqe_addr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */ 01786 /* -------------- */ 01787 pseudo_bit_t reserved5[0x00007]; 01788 pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */ 01789 pseudo_bit_t reserved6[0x00010]; 01790 pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for. 01791 01792 The following values are reported in case of completion with error: 01793 0xFE - For completion with error on Receive Queues 01794 0xFF - For completion with error on Send Queues */ 01795 /* -------------- */ 01796 }; 01797 01798 /* Resize CQ Input Mailbox */ 01799 01800 struct arbelprm_resize_cq_st { /* Little Endian */ 01801 pseudo_bit_t reserved0[0x00020]; 01802 /* -------------- */ 01803 pseudo_bit_t start_addr_h[0x00020]; /* Start address of CQ[63:32]. 01804 Must be aligned on CQE size (32 bytes) */ 01805 /* -------------- */ 01806 pseudo_bit_t start_addr_l[0x00020]; /* Start address of CQ[31:0]. 01807 Must be aligned on CQE size (32 bytes) */ 01808 /* -------------- */ 01809 pseudo_bit_t reserved1[0x00018]; 01810 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ 01811 pseudo_bit_t reserved2[0x00003]; 01812 /* -------------- */ 01813 pseudo_bit_t reserved3[0x00060]; 01814 /* -------------- */ 01815 pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */ 01816 /* -------------- */ 01817 pseudo_bit_t reserved4[0x00100]; 01818 /* -------------- */ 01819 }; 01820 01821 /* MAD_IFC Input Modifier */ 01822 01823 struct arbelprm_mad_ifc_input_modifier_st { /* Little Endian */ 01824 pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ 01825 pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. 01826 Required for trap generation when BKey check is enabled and for global routed packets. */ 01827 pseudo_bit_t reserved0[0x00007]; 01828 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 01829 This field is required for trap generation upon MKey/BKey validation. */ 01830 /* -------------- */ 01831 }; 01832 01833 /* MAD_IFC Input Mailbox */ 01834 01835 struct arbelprm_mad_ifc_st { /* Little Endian */ 01836 pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ 01837 /* -------------- */ 01838 pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. 01839 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01840 pseudo_bit_t reserved0[0x00008]; 01841 /* -------------- */ 01842 pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. 01843 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01844 pseudo_bit_t reserved1[0x00008]; 01845 /* -------------- */ 01846 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 01847 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01848 pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. 01849 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01850 pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. 01851 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01852 pseudo_bit_t reserved2[0x00004]; 01853 pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. 01854 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01855 /* -------------- */ 01856 pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. 01857 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 01858 pseudo_bit_t reserved3[0x00010]; 01859 /* -------------- */ 01860 pseudo_bit_t reserved4[0x00180]; 01861 /* -------------- */ 01862 pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. 01863 Valid if Mad_extended_info bit (in the input modifier) and g bit are set. 01864 Otherwise this field is reserved. */ 01865 /* -------------- */ 01866 pseudo_bit_t reserved5[0x004c0]; 01867 /* -------------- */ 01868 }; 01869 01870 /* Query Debug Message */ 01871 01872 struct arbelprm_query_debug_msg_st { /* Little Endian */ 01873 pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ 01874 /* -------------- */ 01875 pseudo_bit_t v[0x00001]; /* Physical translation is valid */ 01876 pseudo_bit_t reserved0[0x0000b]; 01877 pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ 01878 /* -------------- */ 01879 pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ 01880 /* -------------- */ 01881 pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ 01882 /* -------------- */ 01883 pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ 01884 /* -------------- */ 01885 pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ 01886 /* -------------- */ 01887 pseudo_bit_t reserved1[0x000c0]; 01888 /* -------------- */ 01889 pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ 01890 /* -------------- */ 01891 pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ 01892 /* -------------- */ 01893 pseudo_bit_t reserved2[0x00040]; 01894 /* -------------- */ 01895 pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ 01896 /* -------------- */ 01897 pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ 01898 /* -------------- */ 01899 pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ 01900 /* -------------- */ 01901 pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ 01902 /* -------------- */ 01903 pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ 01904 /* -------------- */ 01905 pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ 01906 /* -------------- */ 01907 pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ 01908 /* -------------- */ 01909 pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ 01910 /* -------------- */ 01911 pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ 01912 /* -------------- */ 01913 pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ 01914 /* -------------- */ 01915 pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ 01916 /* -------------- */ 01917 pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ 01918 /* -------------- */ 01919 pseudo_bit_t buff6_addr[0x00020]; /* Address in firmware area of Trace Buffer 6 */ 01920 /* -------------- */ 01921 pseudo_bit_t buff6_size[0x00020]; /* Size of Trace Buffer 6 */ 01922 /* -------------- */ 01923 pseudo_bit_t buff7_addr[0x00020]; /* Address in firmware area of Trace Buffer 7 */ 01924 /* -------------- */ 01925 pseudo_bit_t buff7_size[0x00020]; /* Size of Trace Buffer 7 */ 01926 /* -------------- */ 01927 pseudo_bit_t reserved3[0x00400]; 01928 /* -------------- */ 01929 }; 01930 01931 /* User Access Region */ 01932 01933 struct arbelprm_uar_st { /* Little Endian */ 01934 struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ 01935 /* -------------- */ 01936 struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */ 01937 /* -------------- */ 01938 pseudo_bit_t reserved0[0x00040]; 01939 /* -------------- */ 01940 struct arbelprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ 01941 /* -------------- */ 01942 pseudo_bit_t reserved1[0x03ec0]; 01943 /* -------------- */ 01944 }; 01945 01946 /* Receive doorbell */ 01947 01948 struct arbelprm_receive_doorbell_st { /* Little Endian */ 01949 pseudo_bit_t reserved0[0x00008]; 01950 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ 01951 pseudo_bit_t reserved1[0x00008]; 01952 /* -------------- */ 01953 pseudo_bit_t reserved2[0x00005]; 01954 pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ 01955 pseudo_bit_t reserved3[0x00002]; 01956 pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ 01957 /* -------------- */ 01958 }; 01959 01960 /* SET_IB Parameters */ 01961 01962 struct arbelprm_set_ib_st { /* Little Endian */ 01963 pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ 01964 pseudo_bit_t reserved0[0x00011]; 01965 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 01966 system_image_guid and sig must be the same for all ports. */ 01967 pseudo_bit_t reserved1[0x0000d]; 01968 /* -------------- */ 01969 pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ 01970 /* -------------- */ 01971 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 01972 Must be the same for both ports. */ 01973 /* -------------- */ 01974 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 01975 Must be the same for both ports. */ 01976 /* -------------- */ 01977 pseudo_bit_t reserved2[0x00180]; 01978 /* -------------- */ 01979 }; 01980 01981 /* Multicast Group Member */ 01982 01983 struct arbelprm_mgm_entry_st { /* Little Endian */ 01984 pseudo_bit_t reserved0[0x00006]; 01985 pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. 01986 The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. 01987 next_gid_index=0 means end of the chain. */ 01988 /* -------------- */ 01989 pseudo_bit_t reserved1[0x00060]; 01990 /* -------------- */ 01991 pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. 01992 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01993 /* -------------- */ 01994 pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. 01995 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01996 /* -------------- */ 01997 pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. 01998 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 01999 /* -------------- */ 02000 pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. 02001 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 02002 /* -------------- */ 02003 struct arbelprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ 02004 /* -------------- */ 02005 struct arbelprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ 02006 /* -------------- */ 02007 struct arbelprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ 02008 /* -------------- */ 02009 struct arbelprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ 02010 /* -------------- */ 02011 struct arbelprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ 02012 /* -------------- */ 02013 struct arbelprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ 02014 /* -------------- */ 02015 struct arbelprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ 02016 /* -------------- */ 02017 struct arbelprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ 02018 /* -------------- */ 02019 }; 02020 02021 /* INIT_IB Parameters */ 02022 02023 struct arbelprm_init_ib_st { /* Little Endian */ 02024 pseudo_bit_t reserved0[0x00004]; 02025 pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. 02026 Legal values are 1,2,4 and 8. */ 02027 pseudo_bit_t port_width_cap[0x00004];/* IB Port Width 02028 1 - 1x 02029 3 - 1x, 4x 02030 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) 02031 else - Reserved */ 02032 pseudo_bit_t mtu_cap[0x00004]; /* Maximum MTU Supported 02033 0x0 - Reserved 02034 0x1 - 256 02035 0x2 - 512 02036 0x3 - 1024 02037 0x4 - 2048 02038 0x5 - 0xF Reserved */ 02039 pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ 02040 pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. 02041 node_guid and ng must be the same for all ports. */ 02042 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 02043 system_image_guid and sig must be the same for all ports. */ 02044 pseudo_bit_t reserved1[0x0000d]; 02045 /* -------------- */ 02046 pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ 02047 pseudo_bit_t reserved2[0x00010]; 02048 /* -------------- */ 02049 pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. 02050 Must be the same for both ports. */ 02051 pseudo_bit_t reserved3[0x00010]; 02052 /* -------------- */ 02053 pseudo_bit_t reserved4[0x00020]; 02054 /* -------------- */ 02055 pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ 02056 /* -------------- */ 02057 pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ 02058 /* -------------- */ 02059 pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set 02060 Must be the same for both ports. */ 02061 /* -------------- */ 02062 pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set 02063 Must be the same for both ports. */ 02064 /* -------------- */ 02065 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 02066 Must be the same for both ports. */ 02067 /* -------------- */ 02068 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 02069 Must be the same for both ports. */ 02070 /* -------------- */ 02071 pseudo_bit_t reserved5[0x006c0]; 02072 /* -------------- */ 02073 }; 02074 02075 /* Query Device Limitations */ 02076 02077 struct arbelprm_query_dev_lim_st { /* Little Endian */ 02078 pseudo_bit_t reserved0[0x00080]; 02079 /* -------------- */ 02080 pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ 02081 pseudo_bit_t reserved1[0x00003]; 02082 pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use 02083 The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ 02084 pseudo_bit_t reserved2[0x00004]; 02085 pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ 02086 pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ 02087 /* -------------- */ 02088 pseudo_bit_t log_max_ee[0x00005]; /* Log2 of the Maximum number of EE contexts supported */ 02089 pseudo_bit_t reserved3[0x00003]; 02090 pseudo_bit_t log2_rsvd_ees[0x00004];/* Log (base 2) of the number of EECs reserved for firmware use 02091 The reserved resources are numbered from 0 to 2^log2_rsvd_ees-1 */ 02092 pseudo_bit_t reserved4[0x00004]; 02093 pseudo_bit_t log_max_srqs[0x00005]; /* Log base 2 of the maximum number of SRQs supported, valid only if SRQ bit is set. 02094 */ 02095 pseudo_bit_t reserved5[0x00007]; 02096 pseudo_bit_t log2_rsvd_srqs[0x00004];/* Log (base 2) of the number of reserved SRQs for firmware use 02097 The reserved resources are numbered from 0 to 2^log2_rsvd_srqs-1 02098 This parameter is valid only if the SRQ bit is set. */ 02099 /* -------------- */ 02100 pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ 02101 pseudo_bit_t reserved6[0x00003]; 02102 pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use 02103 The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ 02104 pseudo_bit_t reserved7[0x00004]; 02105 pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ 02106 pseudo_bit_t reserved8[0x00008]; 02107 /* -------------- */ 02108 pseudo_bit_t log_max_eq[0x00003]; /* Log2 of the Maximum number of EQs */ 02109 pseudo_bit_t reserved9[0x00005]; 02110 pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use 02111 The reserved resources are numbered from 0 to num_rsvd_eqs-1 02112 If 0 - no resources are reserved. */ 02113 pseudo_bit_t reserved10[0x00004]; 02114 pseudo_bit_t log_max_mpts[0x00006]; /* Log (base 2) of the maximum number of MPT entries (the number of Regions/Windows) */ 02115 pseudo_bit_t reserved11[0x00002]; 02116 pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ 02117 /* -------------- */ 02118 pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ 02119 pseudo_bit_t reserved12[0x00002]; 02120 pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use 02121 The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ 02122 pseudo_bit_t reserved13[0x00004]; 02123 pseudo_bit_t log_max_mrw_sz[0x00008];/* Log2 of the Maximum Size of Memory Region/Window */ 02124 pseudo_bit_t reserved14[0x00004]; 02125 pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use 02126 The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 02127 */ 02128 /* -------------- */ 02129 pseudo_bit_t reserved15[0x00020]; 02130 /* -------------- */ 02131 pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ 02132 pseudo_bit_t reserved16[0x0000a]; 02133 pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ 02134 pseudo_bit_t reserved17[0x0000a]; 02135 /* -------------- */ 02136 pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ 02137 pseudo_bit_t reserved18[0x00016]; 02138 pseudo_bit_t log2_rsvd_rdbs[0x00004];/* Log (base 2) of the number of RDB entries reserved for firmware use 02139 The reserved resources are numbered from 0 to 2^log2_rsvd_rdbs-1 */ 02140 /* -------------- */ 02141 pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ 02142 pseudo_bit_t reserved19[0x0001f]; 02143 /* -------------- */ 02144 pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ 02145 pseudo_bit_t max_vl[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */ 02146 pseudo_bit_t max_port_width[0x00004];/* IB Port Width 02147 1 - 1x 02148 3 - 1x, 4x 02149 11 - 1x, 4x or 12x 02150 else - Reserved */ 02151 pseudo_bit_t max_mtu[0x00004]; /* Maximum MTU Supported 02152 0x0 - Reserved 02153 0x1 - 256 02154 0x2 - 512 02155 0x3 - 1024 02156 0x4 - 2048 02157 0x5 - 0xF Reserved */ 02158 pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. 02159 The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ 02160 pseudo_bit_t reserved20[0x0000b]; 02161 /* -------------- */ 02162 pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ 02163 pseudo_bit_t reserved21[0x0001c]; 02164 /* -------------- */ 02165 pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ 02166 pseudo_bit_t reserved22[0x0000c]; 02167 pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported 02168 bit 0 - full bw 02169 bit 1 - 1/4 bw 02170 bit 2 - 1/8 bw 02171 bit 3 - 1/2 bw; */ 02172 /* -------------- */ 02173 pseudo_bit_t reserved23[0x00020]; 02174 /* -------------- */ 02175 pseudo_bit_t rc[0x00001]; /* RC Transport supported */ 02176 pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ 02177 pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ 02178 pseudo_bit_t rd[0x00001]; /* RD Transport Supported */ 02179 pseudo_bit_t raw_ipv6[0x00001]; /* Raw IPv6 Transport Supported */ 02180 pseudo_bit_t raw_ether[0x00001]; /* Raw Ethertype Transport Supported */ 02181 pseudo_bit_t srq[0x00001]; /* SRQ is supported 02182 */ 02183 pseudo_bit_t ipo_ib_checksum[0x00001];/* IP over IB checksum is supported */ 02184 pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ 02185 pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ 02186 pseudo_bit_t reserved24[0x00006]; 02187 pseudo_bit_t mw[0x00001]; /* Memory windows supported */ 02188 pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ 02189 pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ 02190 pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ 02191 pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ 02192 pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ 02193 pseudo_bit_t reserved25[0x00002]; 02194 pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ 02195 pseudo_bit_t r[0x00001]; /* Router mode supported */ 02196 pseudo_bit_t reserved26[0x00006]; 02197 /* -------------- */ 02198 pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). 02199 For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ 02200 pseudo_bit_t reserved27[0x00008]; 02201 pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ 02202 pseudo_bit_t reserved28[0x00006]; 02203 pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use 02204 The reserved resources are numbered from 0 to num_reserved_uars-1 02205 Note that UAR number num_reserved_uars is always for the kernel. */ 02206 /* -------------- */ 02207 pseudo_bit_t reserved29[0x00020]; 02208 /* -------------- */ 02209 pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ 02210 pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ 02211 pseudo_bit_t reserved30[0x00008]; 02212 /* -------------- */ 02213 pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ 02214 pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ 02215 pseudo_bit_t reserved31[0x00008]; 02216 /* -------------- */ 02217 pseudo_bit_t reserved32[0x00040]; 02218 /* -------------- */ 02219 pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ 02220 pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. 02221 The reserved resources are numbered from 0 to num_reserved_mcgs-1 02222 If 0 - no resources are reserved. */ 02223 pseudo_bit_t reserved33[0x00004]; 02224 pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ 02225 pseudo_bit_t reserved34[0x00008]; 02226 /* -------------- */ 02227 pseudo_bit_t log_max_rdds[0x00006]; /* Log2 of the maximum number of RDDs */ 02228 pseudo_bit_t reserved35[0x00006]; 02229 pseudo_bit_t num_rsvd_rdds[0x00004];/* The number of RDDs reserved for firmware use 02230 The reserved resources are numbered from 0 to num_reserved_rdds-1. 02231 If 0 - no resources are reserved. */ 02232 pseudo_bit_t log_max_pd[0x00006]; /* Log2 of the maximum number of PDs */ 02233 pseudo_bit_t reserved36[0x00006]; 02234 pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use 02235 The reserved resources are numbered from 0 to num_reserved_pds-1 02236 If 0 - no resources are reserved. */ 02237 /* -------------- */ 02238 pseudo_bit_t reserved37[0x000c0]; 02239 /* -------------- */ 02240 pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device 02241 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 02242 pseudo_bit_t eec_entry_sz[0x00010]; /* EEC Entry Size for the device 02243 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 02244 /* -------------- */ 02245 pseudo_bit_t eqpc_entry_sz[0x00010];/* Extended QPC entry size for the device 02246 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02247 pseudo_bit_t eeec_entry_sz[0x00010];/* Extended EEC entry size for the device 02248 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02249 /* -------------- */ 02250 pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device 02251 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02252 pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device 02253 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02254 /* -------------- */ 02255 pseudo_bit_t uar_scratch_entry_sz[0x00010];/* UAR Scratchpad Entry Size 02256 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02257 pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device 02258 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 02259 /* -------------- */ 02260 pseudo_bit_t mpt_entry_sz[0x00010]; /* MPT entry size in Bytes for the device. 02261 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 02262 pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. 02263 For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ 02264 /* -------------- */ 02265 pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ 02266 pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: 02267 0 - Type 2A - QP Number Association; or 02268 1 - Type 2B - QP Number and PD Association. */ 02269 pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ 02270 pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. (The device does not supports Block List) */ 02271 pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ 02272 pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ 02273 pseudo_bit_t reserved38[0x00002]; 02274 pseudo_bit_t log_pbl_sz[0x00006]; /* Log2 of the Maximum Physical Buffer List size in Bytes supported by this HCA when invoking the Allocate L_Key verb. 02275 */ 02276 pseudo_bit_t reserved39[0x00012]; 02277 /* -------------- */ 02278 pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ 02279 /* -------------- */ 02280 pseudo_bit_t lamr[0x00001]; /* When set the device requires local attached memory in order to operate. 02281 When set, ICM pages, Firmware Area and ICM auxiliary pages must be allocated in the local attached memory. */ 02282 pseudo_bit_t reserved40[0x0001f]; 02283 /* -------------- */ 02284 pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ 02285 /* -------------- */ 02286 pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ 02287 /* -------------- */ 02288 pseudo_bit_t reserved41[0x002c0]; 02289 /* -------------- */ 02290 }; 02291 02292 /* QUERY_ADAPTER Parameters Block */ 02293 02294 struct arbelprm_query_adapter_st { /* Little Endian */ 02295 pseudo_bit_t reserved0[0x00080]; 02296 /* -------------- */ 02297 pseudo_bit_t reserved1[0x00018]; 02298 pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ 02299 /* -------------- */ 02300 pseudo_bit_t reserved2[0x00060]; 02301 /* -------------- */ 02302 struct arbelprm_vsd_st vsd; 02303 /* -------------- */ 02304 }; 02305 02306 /* QUERY_FW Parameters Block */ 02307 02308 struct arbelprm_query_fw_st { /* Little Endian */ 02309 pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ 02310 pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ 02311 /* -------------- */ 02312 pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ 02313 pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ 02314 /* -------------- */ 02315 pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ 02316 pseudo_bit_t reserved0[0x0000e]; 02317 pseudo_bit_t wqe_h_mode[0x00001]; /* Hermon mode. If '1', then WQE and AV format is the advanced format */ 02318 pseudo_bit_t zb_wq_cq[0x00001]; /* If '1', then ZB mode of WQ and CQ are enabled (i.e. real Memfree PRM is supported) */ 02319 /* -------------- */ 02320 pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ 02321 pseudo_bit_t reserved1[0x00017]; 02322 pseudo_bit_t dt[0x00001]; /* Debug Trace Support 02323 0 - Debug trace is not supported 02324 1 - Debug trace is supported */ 02325 /* -------------- */ 02326 pseudo_bit_t cmd_interface_db[0x00001];/* Set if the device accepts commands by means of special doorbells */ 02327 pseudo_bit_t reserved2[0x0001f]; 02328 /* -------------- */ 02329 pseudo_bit_t reserved3[0x00060]; 02330 /* -------------- */ 02331 pseudo_bit_t clr_int_base_addr_h[0x00020];/* Bits [63:32] of Clear interrupt register physical address. 02332 Points to 64 bit register. */ 02333 /* -------------- */ 02334 pseudo_bit_t clr_int_base_addr_l[0x00020];/* Bits [31:0] of Clear interrupt register physical address. 02335 Points to 64 bit register. */ 02336 /* -------------- */ 02337 pseudo_bit_t reserved4[0x00040]; 02338 /* -------------- */ 02339 pseudo_bit_t error_buf_start_h[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */ 02340 /* -------------- */ 02341 pseudo_bit_t error_buf_start_l[0x00020];/* Read Only buffer for catastrophic error reports (physical address) */ 02342 /* -------------- */ 02343 pseudo_bit_t error_buf_size[0x00020];/* Size in words */ 02344 /* -------------- */ 02345 pseudo_bit_t reserved5[0x00020]; 02346 /* -------------- */ 02347 pseudo_bit_t eq_arm_base_addr_h[0x00020];/* Bits [63:32] of EQ Arm DBs physical address. 02348 Points to 64 bit register. 02349 Setting bit x in the offset, arms EQ number x. 02350 */ 02351 /* -------------- */ 02352 pseudo_bit_t eq_arm_base_addr_l[0x00020];/* Bits [31:0] of EQ Arm DBs physical address. 02353 Points to 64 bit register. 02354 Setting bit x in the offset, arms EQ number x. */ 02355 /* -------------- */ 02356 pseudo_bit_t eq_set_ci_base_addr_h[0x00020];/* Bits [63:32] of EQ Set CI DBs Table physical address. 02357 Points to a the EQ Set CI DBs Table base address. */ 02358 /* -------------- */ 02359 pseudo_bit_t eq_set_ci_base_addr_l[0x00020];/* Bits [31:0] of EQ Set CI DBs Table physical address. 02360 Points to a the EQ Set CI DBs Table base address. */ 02361 /* -------------- */ 02362 pseudo_bit_t cmd_db_dw1[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 1 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02363 pseudo_bit_t cmd_db_dw0[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 0 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02364 /* -------------- */ 02365 pseudo_bit_t cmd_db_dw3[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 3 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02366 pseudo_bit_t cmd_db_dw2[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 2 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02367 /* -------------- */ 02368 pseudo_bit_t cmd_db_dw5[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 5 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02369 pseudo_bit_t cmd_db_dw4[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 4 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02370 /* -------------- */ 02371 pseudo_bit_t cmd_db_dw7[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 7 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02372 pseudo_bit_t cmd_db_dw6[0x00010]; /* offset in bytes from cmd_db_addr_base where DWord 6 of a Command Interface Doorbell should be written. Valid only if CmdInterfaceDb bit is '1' */ 02373 /* -------------- */ 02374 pseudo_bit_t cmd_db_addr_base_h[0x00020];/* High bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */ 02375 /* -------------- */ 02376 pseudo_bit_t cmd_db_addr_base_l[0x00020];/* Low bits of cmd_db_addr_base, which cmd_db_dw offsets refer to. Valid only if CmdInterfaceDb bit is '1' */ 02377 /* -------------- */ 02378 pseudo_bit_t reserved6[0x004c0]; 02379 /* -------------- */ 02380 }; 02381 02382 /* ACCESS_LAM */ 02383 02384 struct arbelprm_access_lam_st { /* Little Endian */ 02385 struct arbelprm_access_lam_inject_errors_st access_lam_inject_errors; 02386 /* -------------- */ 02387 pseudo_bit_t reserved0[0x00080]; 02388 /* -------------- */ 02389 }; 02390 02391 /* ENABLE_LAM Parameters Block */ 02392 02393 struct arbelprm_enable_lam_st { /* Little Endian */ 02394 pseudo_bit_t lam_start_adr_h[0x00020];/* LAM start address [63:32] */ 02395 /* -------------- */ 02396 pseudo_bit_t lam_start_adr_l[0x00020];/* LAM start address [31:0] */ 02397 /* -------------- */ 02398 pseudo_bit_t lam_end_adr_h[0x00020];/* LAM end address [63:32] */ 02399 /* -------------- */ 02400 pseudo_bit_t lam_end_adr_l[0x00020];/* LAM end address [31:0] */ 02401 /* -------------- */ 02402 pseudo_bit_t di[0x00002]; /* Data Integrity Configuration: 02403 00 - none 02404 01 - Parity 02405 10 - ECC Detection Only 02406 11 - ECC With Correction */ 02407 pseudo_bit_t ap[0x00002]; /* Auto Precharge Mode 02408 00 - No auto precharge 02409 01 - Auto precharge per transaction 02410 10 - Auto precharge per 64 bytes 02411 11 - reserved */ 02412 pseudo_bit_t dh[0x00001]; /* When set, LAM is Hidden and can not be accessed directly from the PCI bus. */ 02413 pseudo_bit_t reserved0[0x0001b]; 02414 /* -------------- */ 02415 pseudo_bit_t reserved1[0x00160]; 02416 /* -------------- */ 02417 struct arbelprm_dimminfo_st dimm0; /* Logical DIMM 0 Parameters */ 02418 /* -------------- */ 02419 struct arbelprm_dimminfo_st dimm1; /* Logical DIMM 1 Parameters */ 02420 /* -------------- */ 02421 pseudo_bit_t reserved2[0x00400]; 02422 /* -------------- */ 02423 }; 02424 02425 /* Memory Access Parameters for UD Address Vector Table */ 02426 02427 struct arbelprm_udavtable_memory_parameters_st { /* Little Endian */ 02428 pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ 02429 /* -------------- */ 02430 pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ 02431 pseudo_bit_t reserved0[0x00005]; 02432 pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ 02433 pseudo_bit_t reserved1[0x00002]; 02434 /* -------------- */ 02435 }; 02436 02437 /* INIT_HCA & QUERY_HCA Parameters Block */ 02438 02439 struct arbelprm_init_hca_st { /* Little Endian */ 02440 pseudo_bit_t reserved0[0x00060]; 02441 /* -------------- */ 02442 pseudo_bit_t reserved1[0x00010]; 02443 pseudo_bit_t time_stamp_granularity[0x00008];/* This field controls the granularity in which CQE Timestamp counter is incremented. 02444 The TimeStampGranularity units is 1/4 of a microseconds. (e.g is TimeStampGranularity is configured to 0x2, CQE Timestamp will be incremented every one microsecond) 02445 When sets to Zero, timestamp reporting in the CQE is disabled. 02446 This feature is currently not supported. 02447 */ 02448 pseudo_bit_t hca_core_clock[0x00008];/* Internal Clock Period (in units of 1/16 ns) (QUERY_HCA only) */ 02449 /* -------------- */ 02450 pseudo_bit_t reserved2[0x00008]; 02451 pseudo_bit_t router_qp[0x00010]; /* Upper 16 bit to be used as a QP number for router mode. Low order 8 bits are taken from the TClass field of the incoming packet. 02452 Valid only if RE bit is set */ 02453 pseudo_bit_t reserved3[0x00007]; 02454 pseudo_bit_t re[0x00001]; /* Router Mode Enable 02455 If this bit is set, entire packet (including all headers and ICRC) will be considered as a data payload and will be scattered to memory as specified in the descriptor that is posted on the QP matching the TClass field of packet. */ 02456 /* -------------- */ 02457 pseudo_bit_t udp[0x00001]; /* UD Port Check Enable 02458 0 - Port field in Address Vector is ignored 02459 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ 02460 pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations 02461 0 - Host is Little Endian 02462 1 - Host is Big endian 02463 */ 02464 pseudo_bit_t reserved4[0x00001]; 02465 pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ 02466 pseudo_bit_t sph[0x00001]; /* 0 - SW calculates TCP/UDP Pseudo-Header checksum and inserts it into the TCP/UDP checksum field when sending a packet 02467 1 - HW calculates TCP/UDP Pseudo-Header checksum when sending a packet 02468 */ 02469 pseudo_bit_t rph[0x00001]; /* 0 - Not HW calculation of TCP/UDP Pseudo-Header checksum are done when receiving a packet 02470 1 - HW calculates TCP/UDP Pseudo-Header checksum when receiving a packet 02471 */ 02472 pseudo_bit_t reserved5[0x00002]; 02473 pseudo_bit_t responder_exu[0x00004];/* Indicate the relation between the execution enegines allocation dedicated for responder versus the engines dedicated for reqvester . 02474 responder_exu/16 = (number of responder exu engines)/(total number of engines) 02475 Legal values are 0x0-0xF. 0 is "auto". 02476 02477 */ 02478 pseudo_bit_t reserved6[0x00004]; 02479 pseudo_bit_t wqe_quota[0x0000f]; /* Maximum number of WQEs that are executed prior to preemption of execution unit. 0 - reserved. */ 02480 pseudo_bit_t wqe_quota_en[0x00001]; /* If set - wqe_quota field is used. If cleared - WQE quota is set to "auto" value */ 02481 /* -------------- */ 02482 pseudo_bit_t reserved7[0x00040]; 02483 /* -------------- */ 02484 struct arbelprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters; 02485 /* -------------- */ 02486 pseudo_bit_t reserved8[0x00100]; 02487 /* -------------- */ 02488 struct arbelprm_multicastparam_st multicast_parameters; 02489 /* -------------- */ 02490 pseudo_bit_t reserved9[0x00080]; 02491 /* -------------- */ 02492 struct arbelprm_tptparams_st tpt_parameters; 02493 /* -------------- */ 02494 pseudo_bit_t reserved10[0x00080]; 02495 /* -------------- */ 02496 struct arbelprm_uar_params_st uar_parameters;/* UAR Parameters */ 02497 /* -------------- */ 02498 pseudo_bit_t reserved11[0x00600]; 02499 /* -------------- */ 02500 }; 02501 02502 /* Event Queue Context Table Entry */ 02503 02504 struct arbelprm_eqc_st { /* Little Endian */ 02505 pseudo_bit_t reserved0[0x00008]; 02506 pseudo_bit_t st[0x00004]; /* Event delivery state machine 02507 0x9 - Armed 02508 0xA - Fired 02509 0xB - Always_Armed (auto-rearm) 02510 other - reserved */ 02511 pseudo_bit_t reserved1[0x00005]; 02512 pseudo_bit_t oi[0x00001]; /* Oerrun ignore. 02513 If set, HW will not check EQ full condition when writing new EQEs. */ 02514 pseudo_bit_t tr[0x00001]; /* Translation Required. If set - EQ access undergo address translation. */ 02515 pseudo_bit_t reserved2[0x00005]; 02516 pseudo_bit_t owner[0x00004]; /* 0 - SW ownership 02517 1 - HW ownership 02518 Valid for the QUERY_EQ and HW2SW_EQ commands only */ 02519 pseudo_bit_t status[0x00004]; /* EQ status: 02520 0000 - OK 02521 1010 - EQ write failure 02522 Valid for the QUERY_EQ and HW2SW_EQ commands only */ 02523 /* -------------- */ 02524 pseudo_bit_t start_address_h[0x00020];/* Start Address of Event Queue[63:32]. */ 02525 /* -------------- */ 02526 pseudo_bit_t start_address_l[0x00020];/* Start Address of Event Queue[31:0]. 02527 Must be aligned on 32-byte boundary */ 02528 /* -------------- */ 02529 pseudo_bit_t reserved3[0x00018]; 02530 pseudo_bit_t log_eq_size[0x00005]; /* Amount of entries in this EQ is 2^log_eq_size. 02531 Log_eq_size must be bigger than 1. 02532 Maximum EQ size is 2^17 EQEs (max Log_eq_size is 17). */ 02533 pseudo_bit_t reserved4[0x00003]; 02534 /* -------------- */ 02535 pseudo_bit_t reserved5[0x00020]; 02536 /* -------------- */ 02537 pseudo_bit_t intr[0x00008]; /* Interrupt (message) to be generated to report event to INT layer. 02538 00iiiiii - set to INTA given in QUERY_ADAPTER in order to generate INTA messages on Express. 02539 10jjjjjj - specificies type of interrupt message to be generated (total 64 different messages supported). 02540 All other values are reserved and should not be used. 02541 02542 If interrupt generation is not required, ST field must be set upon creation to Fired state. No EQ arming doorbell should be performed. In this case hardware will not generate any interrupt. */ 02543 pseudo_bit_t reserved6[0x00018]; 02544 /* -------------- */ 02545 pseudo_bit_t pd[0x00018]; /* PD to be used to access EQ */ 02546 pseudo_bit_t reserved7[0x00008]; 02547 /* -------------- */ 02548 pseudo_bit_t lkey[0x00020]; /* Memory key (L-Key) to be used to access EQ */ 02549 /* -------------- */ 02550 pseudo_bit_t reserved8[0x00040]; 02551 /* -------------- */ 02552 pseudo_bit_t consumer_indx[0x00020];/* Contains next entry to be read upon polling the event queue. 02553 Must be initalized to zero while opening EQ */ 02554 /* -------------- */ 02555 pseudo_bit_t producer_indx[0x00020];/* Contains next entry in EQ to be written by the HCA. 02556 Must be initalized to zero while opening EQ. */ 02557 /* -------------- */ 02558 pseudo_bit_t reserved9[0x00080]; 02559 /* -------------- */ 02560 }; 02561 02562 /* Memory Translation Table (MTT) Entry */ 02563 02564 struct arbelprm_mtt_st { /* Little Endian */ 02565 pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 02566 /* -------------- */ 02567 pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ 02568 pseudo_bit_t reserved0[0x0000b]; 02569 pseudo_bit_t ptag_l[0x00014]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 02570 /* -------------- */ 02571 }; 02572 02573 /* Memory Protection Table (MPT) Entry */ 02574 02575 struct arbelprm_mpt_st { /* Little Endian */ 02576 pseudo_bit_t reserved0[0x00008]; 02577 pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ 02578 pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation will be performed for this region */ 02579 pseudo_bit_t lr[0x00001]; /* If set - local read access enabled */ 02580 pseudo_bit_t lw[0x00001]; /* If set - local write access enabled */ 02581 pseudo_bit_t rr[0x00001]; /* If set - remote read access enabled. */ 02582 pseudo_bit_t rw[0x00001]; /* If set - remote write access enabled */ 02583 pseudo_bit_t a[0x00001]; /* If set - remote Atomic access is enabled */ 02584 pseudo_bit_t eb[0x00001]; /* If set - Bind is enabled. Valid for region entry only. */ 02585 pseudo_bit_t reserved1[0x0000c]; 02586 pseudo_bit_t status[0x00004]; /* Region/Window Status 02587 0xF - not valid (SW ownership) 02588 0x3 - FREE state 02589 else - HW ownership 02590 Unbound Type I windows are doneted reg_wnd_len field equals zero. 02591 Unbound Type II windows are donated by Status=FREE. */ 02592 /* -------------- */ 02593 pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 02594 page_size should be less than 20. */ 02595 pseudo_bit_t reserved2[0x00002]; 02596 pseudo_bit_t type[0x00001]; /* Applicable for windows only, must be zero for regions 02597 0 - Type one window 02598 1 - Type two window */ 02599 pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ 02600 /* -------------- */ 02601 pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. 02602 */ 02603 /* -------------- */ 02604 pseudo_bit_t pd[0x00018]; /* Protection Domain */ 02605 pseudo_bit_t reserved3[0x00001]; 02606 pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. 02607 Must be set for type2 windows and non-shared physical memory regions. 02608 Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ 02609 pseudo_bit_t zb[0x00001]; /* When set, this region is Zero Based Region */ 02610 pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ 02611 pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. 02612 Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. 02613 If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail. 02614 */ 02615 pseudo_bit_t reserved4[0x00003]; 02616 /* -------------- */ 02617 pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region/window starts */ 02618 /* -------------- */ 02619 pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region/window starts */ 02620 /* -------------- */ 02621 pseudo_bit_t reg_wnd_len_h[0x00020];/* Region/Window Length[63:32] */ 02622 /* -------------- */ 02623 pseudo_bit_t reg_wnd_len_l[0x00020];/* Region/Window Length[31:0] */ 02624 /* -------------- */ 02625 pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. 02626 On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to. 02627 The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ 02628 /* -------------- */ 02629 pseudo_bit_t win_cnt[0x00020]; /* Number of windows bound to this region. Valid for regions only. 02630 The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ 02631 /* -------------- */ 02632 pseudo_bit_t reserved5[0x00020]; 02633 /* -------------- */ 02634 pseudo_bit_t mtt_adr_h[0x00006]; /* Base (first) address of the MTT relative to MTT base in the ICM */ 02635 pseudo_bit_t reserved6[0x0001a]; 02636 /* -------------- */ 02637 pseudo_bit_t reserved7[0x00003]; 02638 pseudo_bit_t mtt_adr_l[0x0001d]; /* Base (first) address of the MTT relative to MTT base address in the ICM. Must be aligned on 8 bytes. */ 02639 /* -------------- */ 02640 pseudo_bit_t mtt_sz[0x00020]; /* Number of MTT entries allocated for this MR. 02641 When Fast Registration Operations can not be executed on this region (FRE bit is zero) this field is reserved. 02642 When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value is zero, there is no limit for the numbers of MTTs and the HCA does not check this field when executing fast register WQE. */ 02643 /* -------------- */ 02644 pseudo_bit_t reserved8[0x00040]; 02645 /* -------------- */ 02646 }; 02647 02648 /* Completion Queue Context Table Entry */ 02649 02650 struct arbelprm_completion_queue_context_st { /* Little Endian */ 02651 pseudo_bit_t reserved0[0x00008]; 02652 pseudo_bit_t st[0x00004]; /* Event delivery state machine 02653 0x0 - reserved 02654 0x9 - ARMED (Request for Notification) 02655 0x6 - ARMED SOLICITED (Request Solicited Notification) 02656 0xA - FIRED 02657 other - reserved 02658 02659 Must be 0x0 in CQ initialization. 02660 Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 02661 pseudo_bit_t reserved1[0x00005]; 02662 pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. 02663 When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ 02664 pseudo_bit_t reserved2[0x0000a]; 02665 pseudo_bit_t status[0x00004]; /* CQ status 02666 0000 - OK 02667 1001 - CQ overflow 02668 1010 - CQ write failure 02669 Valid for the QUERY_CQ and HW2SW_CQ commands only */ 02670 /* -------------- */ 02671 pseudo_bit_t start_address_h[0x00020];/* Start address of CQ[63:32]. 02672 Must be aligned on CQE size (32 bytes) */ 02673 /* -------------- */ 02674 pseudo_bit_t start_address_l[0x00020];/* Start address of CQ[31:0]. 02675 Must be aligned on CQE size (32 bytes) */ 02676 /* -------------- */ 02677 pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ 02678 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). 02679 Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ 02680 pseudo_bit_t reserved3[0x00003]; 02681 /* -------------- */ 02682 pseudo_bit_t reserved4[0x00020]; 02683 /* -------------- */ 02684 pseudo_bit_t c_eqn[0x00008]; /* Event Queue this CQ reports completion events to. 02685 Valid values are 0 to 63 02686 If configured to value other than 0-63, completion events will not be reported on the CQ. */ 02687 pseudo_bit_t reserved5[0x00018]; 02688 /* -------------- */ 02689 pseudo_bit_t pd[0x00018]; /* Protection Domain to be used to access CQ. 02690 Must be the same PD of the CQ L_Key. */ 02691 pseudo_bit_t reserved6[0x00008]; 02692 /* -------------- */ 02693 pseudo_bit_t l_key[0x00020]; /* Memory key (L_Key) to be used to access CQ */ 02694 /* -------------- */ 02695 pseudo_bit_t last_notified_indx[0x00020];/* Maintained by HW. 02696 Valid for QUERY_CQ and HW2SW_CQ commands only. */ 02697 /* -------------- */ 02698 pseudo_bit_t solicit_producer_indx[0x00020];/* Maintained by HW. 02699 Valid for QUERY_CQ and HW2SW_CQ commands only. 02700 */ 02701 /* -------------- */ 02702 pseudo_bit_t consumer_counter[0x00020];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. 02703 Must be 0x0 in CQ initialization. 02704 Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 02705 /* -------------- */ 02706 pseudo_bit_t producer_counter[0x00020];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. 02707 CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. 02708 Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ 02709 /* -------------- */ 02710 pseudo_bit_t cqn[0x00018]; /* CQ number. Least significant bits are constrained by the position of this CQ in CQC table 02711 Valid for the QUERY_CQ and HW2SW_CQ commands only */ 02712 pseudo_bit_t reserved7[0x00008]; 02713 /* -------------- */ 02714 pseudo_bit_t cq_ci_db_record[0x00020];/* Index in the UAR Context Table Entry. 02715 HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ Consumer Counter doorbell record. 02716 This value can be retrieved from the HW in the QUERY_CQ command. */ 02717 /* -------------- */ 02718 pseudo_bit_t cq_state_db_record[0x00020];/* Index in the UAR Context Table Entry. 02719 HW uses this index as an offset from the UAR Context Table Entry in order to read this CQ state doorbell record. 02720 This value can be retrieved from the HW in the QUERY_CQ command. */ 02721 /* -------------- */ 02722 pseudo_bit_t reserved8[0x00020]; 02723 /* -------------- */ 02724 }; 02725 02726 /* GPIO_event_data */ 02727 02728 struct arbelprm_gpio_event_data_st { /* Little Endian */ 02729 pseudo_bit_t reserved0[0x00060]; 02730 /* -------------- */ 02731 pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 02732 /* -------------- */ 02733 pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 02734 /* -------------- */ 02735 pseudo_bit_t reserved1[0x00020]; 02736 /* -------------- */ 02737 }; 02738 02739 /* Event_data Field - QP/EE Events */ 02740 02741 struct arbelprm_qp_ee_event_st { /* Little Endian */ 02742 pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for */ 02743 pseudo_bit_t reserved0[0x00008]; 02744 /* -------------- */ 02745 pseudo_bit_t reserved1[0x00020]; 02746 /* -------------- */ 02747 pseudo_bit_t reserved2[0x0001c]; 02748 pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field 02749 Not valid on SRQ events */ 02750 pseudo_bit_t reserved3[0x00003]; 02751 /* -------------- */ 02752 pseudo_bit_t reserved4[0x00060]; 02753 /* -------------- */ 02754 }; 02755 02756 /* InfiniHost-III-EX Type0 Configuration Header */ 02757 02758 struct arbelprm_mt25208_type0_st { /* Little Endian */ 02759 pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ 02760 pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode 02761 25218 (decimal) - InfiniHost-III EX mode (the mode described in this manual) 02762 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode 02763 */ 02764 /* -------------- */ 02765 pseudo_bit_t command[0x00010]; /* PCI Command Register */ 02766 pseudo_bit_t status[0x00010]; /* PCI Status Register */ 02767 /* -------------- */ 02768 pseudo_bit_t revision_id[0x00008]; 02769 pseudo_bit_t class_code_hca_class_code[0x00018]; 02770 /* -------------- */ 02771 pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ 02772 pseudo_bit_t latency_timer[0x00008]; 02773 pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ 02774 pseudo_bit_t bist[0x00008]; 02775 /* -------------- */ 02776 pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ 02777 pseudo_bit_t reserved0[0x00010]; 02778 pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ 02779 /* -------------- */ 02780 pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ 02781 /* -------------- */ 02782 pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ 02783 pseudo_bit_t reserved1[0x00010]; 02784 pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ 02785 /* -------------- */ 02786 pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ 02787 /* -------------- */ 02788 pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ 02789 pseudo_bit_t reserved2[0x00010]; 02790 pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 02791 /* -------------- */ 02792 pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 02793 /* -------------- */ 02794 pseudo_bit_t cardbus_cis_pointer[0x00020]; 02795 /* -------------- */ 02796 pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ 02797 pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ 02798 /* -------------- */ 02799 pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 02800 pseudo_bit_t reserved3[0x0000a]; 02801 pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 02802 /* -------------- */ 02803 pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ 02804 pseudo_bit_t reserved4[0x00018]; 02805 /* -------------- */ 02806 pseudo_bit_t reserved5[0x00020]; 02807 /* -------------- */ 02808 pseudo_bit_t interrupt_line[0x00008]; 02809 pseudo_bit_t interrupt_pin[0x00008]; 02810 pseudo_bit_t min_gnt[0x00008]; 02811 pseudo_bit_t max_latency[0x00008]; 02812 /* -------------- */ 02813 pseudo_bit_t reserved6[0x00100]; 02814 /* -------------- */ 02815 pseudo_bit_t msi_cap_id[0x00008]; 02816 pseudo_bit_t msi_next_cap_ptr[0x00008]; 02817 pseudo_bit_t msi_en[0x00001]; 02818 pseudo_bit_t multiple_msg_cap[0x00003]; 02819 pseudo_bit_t multiple_msg_en[0x00003]; 02820 pseudo_bit_t cap_64_bit_addr[0x00001]; 02821 pseudo_bit_t reserved7[0x00008]; 02822 /* -------------- */ 02823 pseudo_bit_t msg_addr_l[0x00020]; 02824 /* -------------- */ 02825 pseudo_bit_t msg_addr_h[0x00020]; 02826 /* -------------- */ 02827 pseudo_bit_t msg_data[0x00010]; 02828 pseudo_bit_t reserved8[0x00010]; 02829 /* -------------- */ 02830 pseudo_bit_t reserved9[0x00080]; 02831 /* -------------- */ 02832 pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ 02833 pseudo_bit_t pm_next_cap_ptr[0x00008]; 02834 pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h 02835 [3] PME clock - 0h 02836 [4] RsvP 02837 [5] Device specific initialization - 0h 02838 [8:6] AUX current - 0h 02839 [9] D1 support - 0h 02840 [10] D2 support - 0h 02841 [15:11] PME support - 0h */ 02842 /* -------------- */ 02843 pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ 02844 pseudo_bit_t pm_control_status_brdg_ext[0x00008]; 02845 pseudo_bit_t data[0x00008]; 02846 /* -------------- */ 02847 pseudo_bit_t reserved10[0x00040]; 02848 /* -------------- */ 02849 pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ 02850 pseudo_bit_t vpd_next_cap_id[0x00008]; 02851 pseudo_bit_t vpd_address[0x0000f]; 02852 pseudo_bit_t f[0x00001]; 02853 /* -------------- */ 02854 pseudo_bit_t vpd_data[0x00020]; 02855 /* -------------- */ 02856 pseudo_bit_t reserved11[0x00040]; 02857 /* -------------- */ 02858 pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ 02859 pseudo_bit_t pciex_next_cap_ptr[0x00008]; 02860 pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h 02861 [7:4] Device/Port Type - 0h 02862 [8] Slot implemented - 0h 02863 [13:9] Interrupt message number 02864 */ 02865 /* -------------- */ 02866 pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h 02867 [4:3] Phantom Function supported - 0h 02868 [5] Extended Tag Filed supported - 0h 02869 [8:6] Endpoint L0s Acceptable Latency - TBD 02870 [11:9] Endpoint L1 Acceptable Latency - TBD 02871 [12] Attention Button Present - configured through InfiniBurn 02872 [13] Attention Indicator Present - configured through InfiniBurn 02873 [14] Power Indicator Present - configured through InfiniBurn 02874 [25:18] Captured Slot Power Limit Value 02875 [27:26] Captured Slot Power Limit Scale */ 02876 /* -------------- */ 02877 pseudo_bit_t device_control[0x00010]; 02878 pseudo_bit_t device_status[0x00010]; 02879 /* -------------- */ 02880 pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h 02881 [9:4] Maximum Link Width - 8h 02882 [11:10] Active State Power Management Support - 3h 02883 [14:12] L0s Exit Latency - TBD 02884 [17:15] L1 Exit Latency - TBD 02885 [31:24] Port Number - 0h */ 02886 /* -------------- */ 02887 pseudo_bit_t link_control[0x00010]; 02888 pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h 02889 [9:4] Negotiated Link Width 02890 [12] Slot clock configuration - 1h */ 02891 /* -------------- */ 02892 pseudo_bit_t reserved12[0x00260]; 02893 /* -------------- */ 02894 pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ 02895 pseudo_bit_t capability_version[0x00004];/* 1h */ 02896 pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ 02897 /* -------------- */ 02898 pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status 02899 4 Data Link Protocol Error Status 02900 12 Poisoned TLP Status 02901 13 Flow Control Protocol Error Status 02902 14 Completion Timeout Status 02903 15 Completer Abort Status 02904 16 Unexpected Completion Status 02905 17 Receiver Overflow Status 02906 18 Malformed TLP Status 02907 19 ECRC Error Status 02908 20 Unsupported Request Error Status */ 02909 /* -------------- */ 02910 pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask 02911 4 Data Link Protocol Error Mask 02912 12 Poisoned TLP Mask 02913 13 Flow Control Protocol Error Mask 02914 14 Completion Timeout Mask 02915 15 Completer Abort Mask 02916 16 Unexpected Completion Mask 02917 17 Receiver Overflow Mask 02918 18 Malformed TLP Mask 02919 19 ECRC Error Mask 02920 20 Unsupported Request Error Mask */ 02921 /* -------------- */ 02922 pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity 02923 4 Data Link Protocol Error Severity 02924 12 Poisoned TLP Severity 02925 13 Flow Control Protocol Error Severity 02926 14 Completion Timeout Severity 02927 15 Completer Abort Severity 02928 16 Unexpected Completion Severity 02929 17 Receiver Overflow Severity 02930 18 Malformed TLP Severity 02931 19 ECRC Error Severity 02932 20 Unsupported Request Error Severity */ 02933 /* -------------- */ 02934 pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status 02935 6 Bad TLP Status 02936 7 Bad DLLP Status 02937 8 REPLAY_NUM Rollover Status 02938 12 Replay Timer Timeout Status */ 02939 /* -------------- */ 02940 pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask 02941 6 Bad TLP Mask 02942 7 Bad DLLP Mask 02943 8 REPLAY_NUM Rollover Mask 02944 12 Replay Timer Timeout Mask */ 02945 /* -------------- */ 02946 pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; 02947 /* -------------- */ 02948 struct arbelprm_header_log_register_st header_log_register; 02949 /* -------------- */ 02950 pseudo_bit_t reserved13[0x006a0]; 02951 /* -------------- */ 02952 }; 02953 02954 /* Event Data Field - Performance Monitor */ 02955 02956 struct arbelprm_performance_monitor_event_st { /* Little Endian */ 02957 struct arbelprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ 02958 /* -------------- */ 02959 pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC 02960 0x02 - RQPC 02961 0x03 - CQC 02962 0x04 - Rkey 02963 0x05 - TLB 02964 0x06 - port0 02965 0x07 - port1 */ 02966 pseudo_bit_t reserved0[0x00018]; 02967 /* -------------- */ 02968 pseudo_bit_t reserved1[0x00040]; 02969 /* -------------- */ 02970 }; 02971 02972 /* Event_data Field - Page Faults */ 02973 02974 struct arbelprm_page_fault_event_data_st { /* Little Endian */ 02975 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 02976 /* -------------- */ 02977 pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 02978 /* -------------- */ 02979 pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ 02980 /* -------------- */ 02981 pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ 02982 pseudo_bit_t reserved0[0x00003]; 02983 pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ 02984 pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ 02985 pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ 02986 pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ 02987 pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ 02988 /* -------------- */ 02989 pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ 02990 pseudo_bit_t reserved1[0x00008]; 02991 /* -------------- */ 02992 pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ 02993 /* -------------- */ 02994 }; 02995 02996 /* WQE segments format */ 02997 02998 struct arbelprm_wqe_segment_st { /* Little Endian */ 02999 struct arbelprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ 03000 /* -------------- */ 03001 pseudo_bit_t reserved0[0x00280]; 03002 /* -------------- */ 03003 struct arbelprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ 03004 /* -------------- */ 03005 pseudo_bit_t reserved1[0x00100]; 03006 /* -------------- */ 03007 struct arbelprm_wqe_segment_ctrl_recv_st recv_wqe_segment_ctrl;/* Receive segment format */ 03008 /* -------------- */ 03009 pseudo_bit_t reserved2[0x00080]; 03010 /* -------------- */ 03011 }; 03012 03013 /* Event_data Field - Port State Change */ 03014 03015 struct arbelprm_port_state_change_st { /* Little Endian */ 03016 pseudo_bit_t reserved0[0x00040]; 03017 /* -------------- */ 03018 pseudo_bit_t reserved1[0x0001c]; 03019 pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ 03020 pseudo_bit_t reserved2[0x00002]; 03021 /* -------------- */ 03022 pseudo_bit_t reserved3[0x00060]; 03023 /* -------------- */ 03024 }; 03025 03026 /* Event_data Field - Completion Queue Error */ 03027 03028 struct arbelprm_completion_queue_error_st { /* Little Endian */ 03029 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 03030 pseudo_bit_t reserved0[0x00008]; 03031 /* -------------- */ 03032 pseudo_bit_t reserved1[0x00020]; 03033 /* -------------- */ 03034 pseudo_bit_t syndrome[0x00008]; /* Error syndrome 03035 0x01 - CQ overrun 03036 0x02 - CQ access violation error */ 03037 pseudo_bit_t reserved2[0x00018]; 03038 /* -------------- */ 03039 pseudo_bit_t reserved3[0x00060]; 03040 /* -------------- */ 03041 }; 03042 03043 /* Event_data Field - Completion Event */ 03044 03045 struct arbelprm_completion_event_st { /* Little Endian */ 03046 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 03047 pseudo_bit_t reserved0[0x00008]; 03048 /* -------------- */ 03049 pseudo_bit_t reserved1[0x000a0]; 03050 /* -------------- */ 03051 }; 03052 03053 /* Event Queue Entry */ 03054 03055 struct arbelprm_event_queue_entry_st { /* Little Endian */ 03056 pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. 03057 Defined for events which have sub types, zero elsewhere. */ 03058 pseudo_bit_t reserved0[0x00008]; 03059 pseudo_bit_t event_type[0x00008]; /* Event Type */ 03060 pseudo_bit_t reserved1[0x00008]; 03061 /* -------------- */ 03062 pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ 03063 /* -------------- */ 03064 pseudo_bit_t reserved2[0x00007]; 03065 pseudo_bit_t owner[0x00001]; /* Owner of the entry 03066 0 SW 03067 1 HW */ 03068 pseudo_bit_t reserved3[0x00018]; 03069 /* -------------- */ 03070 }; 03071 03072 /* QP/EE State Transitions Command Parameters */ 03073 03074 struct arbelprm_qp_ee_state_transitions_st { /* Little Endian */ 03075 pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ 03076 /* -------------- */ 03077 pseudo_bit_t reserved0[0x00020]; 03078 /* -------------- */ 03079 struct arbelprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data */ 03080 /* -------------- */ 03081 pseudo_bit_t reserved1[0x009c0]; 03082 /* -------------- */ 03083 }; 03084 03085 /* Completion Queue Entry Format */ 03086 03087 struct arbelprm_completion_queue_entry_st { /* Little Endian */ 03088 pseudo_bit_t my_qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 03089 pseudo_bit_t reserved0[0x00004]; 03090 pseudo_bit_t ver[0x00004]; /* CQE version. 03091 0 for InfiniHost-III-EX */ 03092 /* -------------- */ 03093 pseudo_bit_t my_ee[0x00018]; /* EE context (for RD only). 03094 Invalid for Bind and Nop operation on RD. 03095 For non RD services this filed reports the CQE timestamp. The Timestamp is a free running counter that is incremented every TimeStampGranularity tick. The counter rolls-over when it reaches saturation. TimeStampGranularity is configured in the INIT_HCA command. This feature is currently not supported. 03096 */ 03097 pseudo_bit_t checksum_15_8[0x00008];/* Checksum[15:8] - See IPoverIB checksum offloading chapter */ 03098 /* -------------- */ 03099 pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number. Valid in Responder CQE only for Datagram QP. */ 03100 pseudo_bit_t checksum_7_0[0x00008]; /* Checksum[7:0] - See IPoverIB checksum offloading chapter */ 03101 /* -------------- */ 03102 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID of the message. Valid in Responder of UD QP CQE only. */ 03103 pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits - these are the lowemost LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. 03104 Valid in responder of UD QP CQE only. 03105 Invalid if incoming message DLID is the permissive LID or incoming message is multicast. */ 03106 pseudo_bit_t g[0x00001]; /* GRH present indicator. Valid in Responder of UD QP CQE only. */ 03107 pseudo_bit_t ipok[0x00001]; /* IP OK - See IPoverIB checksum offloading chapter */ 03108 pseudo_bit_t reserved1[0x00003]; 03109 pseudo_bit_t sl[0x00004]; /* Service Level of the message. Valid in Responder of UD QP CQE only. */ 03110 /* -------------- */ 03111 pseudo_bit_t immediate_ethertype_pkey_indx_eecredits[0x00020];/* Valid for receive queue completion only. 03112 If Opcode field indicates that this was send/write with immediate, this field contains immediate field of the packet. 03113 If completion corresponds to RAW receive queue, bits 15:0 contain Ethertype field of the packet. 03114 If completion corresponds to GSI receive queue, bits 31:16 contain index in PKey table that matches PKey of the message arrived. 03115 If Opcode field indicates that this was send and invalidate, this field contains the key that was invalidated. 03116 For CQE of send queue of the reliable connection service (but send and invalide), bits [4:0] of this field contain the encoded EEcredits received in last ACK of the message. */ 03117 /* -------------- */ 03118 pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data actually transferred (valid for receive queue completions only) */ 03119 /* -------------- */ 03120 pseudo_bit_t reserved2[0x00006]; 03121 pseudo_bit_t wqe_adr[0x0001a]; /* Bits 31:6 of WQE virtual address completion is reported for. The 6 least significant bits are zero. */ 03122 /* -------------- */ 03123 pseudo_bit_t reserved3[0x00007]; 03124 pseudo_bit_t owner[0x00001]; /* Owner field. Zero value of this field means SW ownership of CQE. */ 03125 pseudo_bit_t reserved4[0x0000f]; 03126 pseudo_bit_t s[0x00001]; /* If set, completion is reported for Send queue, if cleared - receive queue. */ 03127 pseudo_bit_t opcode[0x00008]; /* The opcode of WQE completion is reported for. 03128 For CQEs corresponding to send completion, NOPCODE field of the WQE is copied to this field. 03129 For CQEs corresponding to receive completions, opcode field of last packet in the message copied to this field. 03130 For CQEs corresponding to the receive queue of QPs mapped to QP1, the opcode will be SEND with Immediate (messages are guaranteed to be SEND only) 03131 03132 The following values are reported in case of completion with error: 03133 0xFE - For completion with error on Receive Queues 03134 0xFF - For completion with error on Send Queues */ 03135 /* -------------- */ 03136 }; 03137 03138 /* */ 03139 03140 struct arbelprm_ecc_detect_event_data_st { /* Little Endian */ 03141 pseudo_bit_t reserved0[0x00080]; 03142 /* -------------- */ 03143 pseudo_bit_t cause_lsb[0x00001]; 03144 pseudo_bit_t reserved1[0x00002]; 03145 pseudo_bit_t cause_msb[0x00001]; 03146 pseudo_bit_t reserved2[0x00002]; 03147 pseudo_bit_t err_rmw[0x00001]; 03148 pseudo_bit_t err_src_id[0x00003]; 03149 pseudo_bit_t err_da[0x00002]; 03150 pseudo_bit_t err_ba[0x00002]; 03151 pseudo_bit_t reserved3[0x00011]; 03152 pseudo_bit_t overflow[0x00001]; 03153 /* -------------- */ 03154 pseudo_bit_t err_ra[0x00010]; 03155 pseudo_bit_t err_ca[0x00010]; 03156 /* -------------- */ 03157 }; 03158 03159 /* Event_data Field - ECC Detection Event */ 03160 03161 struct arbelprm_scrubbing_event_st { /* Little Endian */ 03162 pseudo_bit_t reserved0[0x00080]; 03163 /* -------------- */ 03164 pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: 03165 single ECC error in the 64bit lsb data, on the rise edge of the clock */ 03166 pseudo_bit_t reserved1[0x00002]; 03167 pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: 03168 single ECC error in the 64bit msb data, on the fall edge of the clock */ 03169 pseudo_bit_t reserved2[0x00002]; 03170 pseudo_bit_t err_rmw[0x00001]; /* transaction type: 03171 0 - read 03172 1 - read/modify/write */ 03173 pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ 03174 pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ 03175 pseudo_bit_t err_ba[0x00002]; /* Error bank address */ 03176 pseudo_bit_t reserved3[0x00011]; 03177 pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ 03178 /* -------------- */ 03179 pseudo_bit_t err_ra[0x00010]; /* Error row address */ 03180 pseudo_bit_t err_ca[0x00010]; /* Error column address */ 03181 /* -------------- */ 03182 }; 03183 03184 /* Miscellaneous Counters */ 03185 03186 struct arbelprm_misc_counters_st { /* Little Endian */ 03187 pseudo_bit_t ddr_scan_cnt[0x00020]; /* Number of times whole of LAM was scanned */ 03188 /* -------------- */ 03189 pseudo_bit_t reserved0[0x007e0]; 03190 /* -------------- */ 03191 }; 03192 03193 /* LAM_EN Output Parameter */ 03194 03195 struct arbelprm_lam_en_out_param_st { /* Little Endian */ 03196 pseudo_bit_t reserved0[0x00040]; 03197 /* -------------- */ 03198 }; 03199 03200 /* Extended_Completion_Queue_Entry */ 03201 03202 struct arbelprm_extended_completion_queue_entry_st { /* Little Endian */ 03203 pseudo_bit_t reserved0[0x00020]; 03204 /* -------------- */ 03205 }; 03206 03207 /* */ 03208 03209 struct arbelprm_eq_cmd_doorbell_st { /* Little Endian */ 03210 pseudo_bit_t reserved0[0x00020]; 03211 /* -------------- */ 03212 }; 03213 03214 /* 0 */ 03215 03216 struct arbelprm_arbel_prm_st { /* Little Endian */ 03217 struct arbelprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ 03218 /* -------------- */ 03219 pseudo_bit_t reserved0[0x7ff00]; 03220 /* -------------- */ 03221 struct arbelprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ 03222 /* -------------- */ 03223 pseudo_bit_t reserved1[0x7f000]; 03224 /* -------------- */ 03225 struct arbelprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ 03226 /* -------------- */ 03227 pseudo_bit_t reserved2[0x7ff00]; 03228 /* -------------- */ 03229 struct arbelprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ 03230 /* -------------- */ 03231 pseudo_bit_t reserved3[0x7ff40]; 03232 /* -------------- */ 03233 struct arbelprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ 03234 /* -------------- */ 03235 pseudo_bit_t reserved4[0x7ff40]; 03236 /* -------------- */ 03237 struct arbelprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ 03238 /* -------------- */ 03239 pseudo_bit_t reserved5[0x7ff40]; 03240 /* -------------- */ 03241 struct arbelprm_wqe_segment_st wqe_segment;/* WQE segments format */ 03242 /* -------------- */ 03243 pseudo_bit_t reserved6[0x7f000]; 03244 /* -------------- */ 03245 struct arbelprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ 03246 /* -------------- */ 03247 pseudo_bit_t reserved7[0x7ff40]; 03248 /* -------------- */ 03249 struct arbelprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ 03250 /* -------------- */ 03251 pseudo_bit_t reserved8[0xfff20]; 03252 /* -------------- */ 03253 struct arbelprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ 03254 /* -------------- */ 03255 pseudo_bit_t reserved9[0x7f000]; 03256 /* -------------- */ 03257 struct arbelprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ 03258 /* -------------- */ 03259 pseudo_bit_t reserved10[0x00040]; 03260 /* -------------- */ 03261 struct arbelprm_gpio_event_data_st gpio_event_data; 03262 /* -------------- */ 03263 pseudo_bit_t reserved11[0x7fe40]; 03264 /* -------------- */ 03265 struct arbelprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 03266 /* -------------- */ 03267 pseudo_bit_t reserved12[0x7ff00]; 03268 /* -------------- */ 03269 struct arbelprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ 03270 /* -------------- */ 03271 pseudo_bit_t reserved13[0x7fa00]; 03272 /* -------------- */ 03273 struct arbelprm_address_path_st address_path;/* Address Path */ 03274 /* -------------- */ 03275 pseudo_bit_t reserved14[0x7ff00]; 03276 /* -------------- */ 03277 struct arbelprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ 03278 /* -------------- */ 03279 pseudo_bit_t reserved15[0x7fe00]; 03280 /* -------------- */ 03281 struct arbelprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ 03282 /* -------------- */ 03283 pseudo_bit_t reserved16[0x7fe00]; 03284 /* -------------- */ 03285 struct arbelprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ 03286 /* -------------- */ 03287 pseudo_bit_t reserved17[0x7ffc0]; 03288 /* -------------- */ 03289 struct arbelprm_eqc_st eqc; /* Event Queue Context Table Entry */ 03290 /* -------------- */ 03291 pseudo_bit_t reserved18[0x7fe00]; 03292 /* -------------- */ 03293 struct arbelprm_performance_monitors_st performance_monitors;/* Performance Monitors */ 03294 /* -------------- */ 03295 pseudo_bit_t reserved19[0x7ff80]; 03296 /* -------------- */ 03297 struct arbelprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ 03298 /* -------------- */ 03299 pseudo_bit_t reserved20[0xfff20]; 03300 /* -------------- */ 03301 struct arbelprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ 03302 /* -------------- */ 03303 pseudo_bit_t reserved21[0x7f000]; 03304 /* -------------- */ 03305 struct arbelprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ 03306 /* -------------- */ 03307 pseudo_bit_t reserved22[0x7fc00]; 03308 /* -------------- */ 03309 struct arbelprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ 03310 /* -------------- */ 03311 pseudo_bit_t reserved23[0x7ffc0]; 03312 /* -------------- */ 03313 struct arbelprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ 03314 /* -------------- */ 03315 pseudo_bit_t reserved24[0x7ff00]; 03316 /* -------------- */ 03317 struct arbelprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ 03318 /* -------------- */ 03319 pseudo_bit_t reserved25[0x7ff00]; 03320 /* -------------- */ 03321 struct arbelprm_enable_lam_st enable_lam;/* ENABLE_LAM Parameters Block */ 03322 /* -------------- */ 03323 struct arbelprm_access_lam_st access_lam; 03324 /* -------------- */ 03325 pseudo_bit_t reserved26[0x7f700]; 03326 /* -------------- */ 03327 struct arbelprm_dimminfo_st dimminfo;/* Logical DIMM Information */ 03328 /* -------------- */ 03329 pseudo_bit_t reserved27[0x7ff00]; 03330 /* -------------- */ 03331 struct arbelprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ 03332 /* -------------- */ 03333 pseudo_bit_t reserved28[0x7f800]; 03334 /* -------------- */ 03335 struct arbelprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ 03336 /* -------------- */ 03337 pseudo_bit_t reserved29[0x7f800]; 03338 /* -------------- */ 03339 struct arbelprm_query_dev_lim_st query_dev_lim;/* Query Device Limitations */ 03340 /* -------------- */ 03341 pseudo_bit_t reserved30[0x7f800]; 03342 /* -------------- */ 03343 struct arbelprm_uar_params_st uar_params;/* UAR Parameters */ 03344 /* -------------- */ 03345 pseudo_bit_t reserved31[0x7ff00]; 03346 /* -------------- */ 03347 struct arbelprm_init_ib_st init_ib; /* INIT_IB Parameters */ 03348 /* -------------- */ 03349 pseudo_bit_t reserved32[0x7f800]; 03350 /* -------------- */ 03351 struct arbelprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ 03352 /* -------------- */ 03353 pseudo_bit_t reserved33[0x7fe00]; 03354 /* -------------- */ 03355 struct arbelprm_set_ib_st set_ib; /* SET_IB Parameters */ 03356 /* -------------- */ 03357 pseudo_bit_t reserved34[0x7fe00]; 03358 /* -------------- */ 03359 struct arbelprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ 03360 /* -------------- */ 03361 pseudo_bit_t reserved35[0x7ff80]; 03362 /* -------------- */ 03363 struct arbelprm_send_doorbell_st send_doorbell;/* Send doorbell */ 03364 /* -------------- */ 03365 pseudo_bit_t reserved36[0x7ffc0]; 03366 /* -------------- */ 03367 struct arbelprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ 03368 /* -------------- */ 03369 pseudo_bit_t reserved37[0x7ffc0]; 03370 /* -------------- */ 03371 struct arbelprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ 03372 /* -------------- */ 03373 pseudo_bit_t reserved38[0xfffc0]; 03374 /* -------------- */ 03375 struct arbelprm_uar_st uar; /* User Access Region */ 03376 /* -------------- */ 03377 pseudo_bit_t reserved39[0x7c000]; 03378 /* -------------- */ 03379 struct arbelprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ 03380 /* -------------- */ 03381 pseudo_bit_t reserved40[0x7ffe0]; 03382 /* -------------- */ 03383 struct arbelprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ 03384 /* -------------- */ 03385 pseudo_bit_t reserved41[0x7f800]; 03386 /* -------------- */ 03387 struct arbelprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ 03388 /* -------------- */ 03389 pseudo_bit_t reserved42[0x00900]; 03390 /* -------------- */ 03391 struct arbelprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ 03392 /* -------------- */ 03393 pseudo_bit_t reserved43[0x7e6e0]; 03394 /* -------------- */ 03395 struct arbelprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ 03396 /* -------------- */ 03397 pseudo_bit_t reserved44[0x7fe00]; 03398 /* -------------- */ 03399 struct arbelprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ 03400 /* -------------- */ 03401 pseudo_bit_t reserved45[0x7ff00]; 03402 /* -------------- */ 03403 struct arbelprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ 03404 /* -------------- */ 03405 pseudo_bit_t reserved46[0x7ff40]; 03406 /* -------------- */ 03407 struct arbelprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ 03408 /* -------------- */ 03409 pseudo_bit_t reserved47[0x7f000]; 03410 /* -------------- */ 03411 struct arbelprm_performance_counters_st performance_counters;/* Performance Counters */ 03412 /* -------------- */ 03413 pseudo_bit_t reserved48[0x9ff800]; 03414 /* -------------- */ 03415 struct arbelprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 03416 /* -------------- */ 03417 pseudo_bit_t reserved49[0x7ff00]; 03418 /* -------------- */ 03419 struct arbelprm_pbl_st pbl; /* Physical Buffer List */ 03420 /* -------------- */ 03421 pseudo_bit_t reserved50[0x7ff00]; 03422 /* -------------- */ 03423 struct arbelprm_srq_context_st srq_context;/* SRQ Context */ 03424 /* -------------- */ 03425 pseudo_bit_t reserved51[0x7fe80]; 03426 /* -------------- */ 03427 struct arbelprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ 03428 /* -------------- */ 03429 pseudo_bit_t reserved52[0x7f800]; 03430 /* -------------- */ 03431 struct arbelprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ 03432 /* -------------- */ 03433 pseudo_bit_t reserved53[0x7ff80]; 03434 /* -------------- */ 03435 struct arbelprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ 03436 /* -------------- */ 03437 pseudo_bit_t reserved54[0x7ffc0]; 03438 /* -------------- */ 03439 struct arbelprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ 03440 /* -------------- */ 03441 pseudo_bit_t reserved55[0x7ffc0]; 03442 /* -------------- */ 03443 struct arbelprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ 03444 /* -------------- */ 03445 pseudo_bit_t reserved56[0x1fffc0]; 03446 /* -------------- */ 03447 struct arbelprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ 03448 /* -------------- */ 03449 struct arbelprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ 03450 /* -------------- */ 03451 pseudo_bit_t reserved57[0x01000]; 03452 /* -------------- */ 03453 struct arbelprm_eq_arm_db_region_st eq_arm_db_region;/* EQ Arm Doorbell Region */ 03454 /* -------------- */ 03455 pseudo_bit_t reserved58[0x00fc0]; 03456 /* -------------- */ 03457 struct arbelprm_clr_int_st clr_int; /* Clear Interrupt Register */ 03458 /* -------------- */ 03459 pseudo_bit_t reserved59[0xffcfc0]; 03460 /* -------------- */ 03461 }; 03462 #endif /* H_prefix_arbelprm_bits_fixnames_MT25218_PRM_csp_H */
1.5.7.1